From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 16E7E3858D37; Sat, 29 Apr 2023 03:51:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16E7E3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682740314; bh=HqnlT+592Fjzi1fa7BGOdn3KmZ1surYpdosGyPs9Xr8=; h=From:To:Subject:Date:From; b=tjhcwfXpbOJeXjuSvdbVdydBxkGr6bJ0lDkIG2MFJjUZBZf2xe0QpwUGyC9ND+Gvn yQxf+Ri2rtlTGyZa+3codc1ImXJDqa20DXGMjUv0cnhh+OTc9sraHeCPluXGvlXoA+ JrWxEyLmLSSHGQ8WtWQRj9rHxYC39MisAtsd0GQY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow constant element vec_extract to be converted to floating point X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 32a7c2ff7d8ef24e262125ae233cd4ccbc5d9250 X-Git-Newrev: 7c7742d904f6d629bba309a7e854d28d3d0d0d30 Message-Id: <20230429035154.16E7E3858D37@sourceware.org> Date: Sat, 29 Apr 2023 03:51:54 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7c7742d904f6d629bba309a7e854d28d3d0d0d30 commit 7c7742d904f6d629bba309a7e854d28d3d0d0d30 Author: Michael Meissner Date: Fri Apr 28 23:51:29 2023 -0400 Allow constant element vec_extract to be converted to floating point This patch allows vec_extract of the following types to be converted to floating point by loading the value directly to the vector register, and then doing the conversion instead of loading the value to a GPR and then doing a direct move: vector int vector unsigned int vector unsigned short vector unsigned char 2023-04-28 Michael Meissner gcc/ * config/rs6000/rs6000.md (fp_int_extend): New code attribute. * config/rs6000/vsx.md (vsx_extract_v4si_load_to_): New * insn. * vsx_extract__load_to_uns: New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-char-2.c: New file. * gcc.target/powerpc/vec-extract-mem-int-4.c: New file. * gcc.target/powerpc/vec-extract-mem-int_5.c: New file. * gcc.target/powerpc/vec-extract-mem-short-4.c: New file. Diff: --- gcc/config/rs6000/rs6000.md | 3 ++ gcc/config/rs6000/vsx.md | 50 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-char-2.c | 41 ++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-4.c | 40 +++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-5.c | 40 +++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-short-4.c | 41 ++++++++++++++++++ 6 files changed, 215 insertions(+) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7d6c94aee5b..b1e3750f528 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -664,6 +664,9 @@ (float "") (unsigned_float "uns")]) +(define_code_attr fp_int_extend [(float "sign_extend") + (unsigned_float "zero_extend")]) + ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. (define_mode_attr wd [(QI "b") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 8fc56bff892..559a7034367 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4113,6 +4113,56 @@ (set_attr "length" "*, *, 8, *, 8") (set_attr "isa" "*, *, *, p9v, p9v")]) +;; Fold extracting a V4SI element with a constant element with either sign or +;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID. +(define_insn_and_split "*vsx_extract_v4si_load_to_" + [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") + (any_float:SFDF + (vec_select:SI + (match_operand:V4SI 1 "memory_operand" "Z,Q") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")])))) + (clobber (match_scratch:DI 3 "=X,&b")) + (clobber (match_scratch:DI 4 "=wa,wa"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 4) + (:DI (match_dup 5))) + (set (match_dup 0) + (float:SFDF (match_dup 4)))] +{ + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + +;; Fold extracting a V8HI/V16QI element with a constant element with zero +;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID +(define_insn_and_split "*vsx_extract__load_to_uns" + [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") + (unsigned_float:SFDF + (vec_select: + (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q") + (parallel [(match_operand:QI 2 "const_int_operand" "O,n")])))) + (clobber (match_scratch:DI 3 "=X,&b")) + (clobber (match_scratch:DI 4 "=v,v"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_P9_VECTOR" + "#" + "&& reload_completed" + [(set (match_dup 4) + (zero_extend:DI (match_dup 5))) + (set (match_dup 0) + (float:SFDF (match_dup 4)))] +{ + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + ;; Fold extracting a V8HI element with a constant element with sign extension ;; to either DImode or SImode. ;; Reg: Ele: Addr: need scratch diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c new file mode 100644 index 00000000000..a537dfe2350 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + QImode and convert it to unsigned floating point, by loading the value + directly to a vector register, rather than loading up a GPR and transfering + the result to a vector register. This tests whether the ISA 3.0 LXSIBZX + instruction is generated. */ + +#include + +double +extract_dbl_uns_v16qi_0 (vector unsigned char *p) +{ + return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */ +} + +double +extract_dbl_uns_v16qi_1 (vector unsigned char *p) +{ + return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */ +} + +float +extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */ +} + +float +extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */ +} + +/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c new file mode 100644 index 00000000000..95805325e9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and convert it to unsigned floating point, by loading the value + directly to a vector register, rather than loading up a GPR and transfering + the result to a vector register. */ + +#include + +double +extract_dbl_uns_v4si_0 (vector unsigned int *p) +{ + return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ +} + +double +extract_dbl_uns_v4si_1 (vector unsigned int *p) +{ + return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ +} + +float +extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ +} + +float +extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ +} + +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c new file mode 100644 index 00000000000..3cf9bafd4f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and convert it to signed floating point, by loading the value + directly to a vector register, rather than loading up a GPR and transfering + the result to a vector register. */ + +#include + +double +extract_dbl_sign_v4si_0 (vector int *p) +{ + return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ +} + +double +extract_dbl_sign_v4si_1 (vector int *p) +{ + return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ +} + +float +extract_flt_sign_v4si_element_0_index_4 (vector int *p) +{ + return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ +} + +float +extract_flt_sign_v4si_element_3_index_4 (vector int *p) +{ + return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ +} + +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c new file mode 100644 index 00000000000..533a80d3d52 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + HImode and convert it to unsigned floating point, by loading the value + directly to a vector register, rather than loading up a GPR and transfering + the result to a vector register. This tests whether the ISA 3.0 LXSIHZX + instruction is generated. */ + +#include + +double +extract_dbl_uns_v8hi_0 (vector unsigned short *p) +{ + return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */ +} + +double +extract_dbl_uns_v8hi_1 (vector unsigned short *p) +{ + return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */ +} + +float +extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */ +} + +float +extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */ +} + +/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsr} } } */