From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3F91C3858D1E; Mon, 1 May 2023 20:18:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3F91C3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682972319; bh=GUPUwWeCHEJCUsSv5VqAmi17LBLHo99Pp1z2POvDaRs=; h=From:To:Subject:Date:From; b=TLWaLmKO7FOrdr5j7t1r72f+pICJkEz2Wbw7x4EYBXfg+dxX2LRuXMTvfa707CFa4 kFMgdDt1i3Rimb062p3fwsohaY8PUaZ9CU6zN2Yl73/D6wpyFlnEqtyY09i02nkPOv UQeL3H8ByGce5hHzEAYCR0i+Mrq62oM5bw5VkP7M= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work120)] Improve 64->128 bit zero extension on PowerPC X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work120 X-Git-Oldrev: 133810eb00cc9e20e28fb7a69d89a16fa88e88e7 X-Git-Newrev: 386950384507b51861dc2c504768b643138218d6 Message-Id: <20230501201839.3F91C3858D1E@sourceware.org> Date: Mon, 1 May 2023 20:18:39 +0000 (GMT) List-Id: https://gcc.gnu.org/g:386950384507b51861dc2c504768b643138218d6 commit 386950384507b51861dc2c504768b643138218d6 Author: Michael Meissner Date: Mon May 1 16:18:13 2023 -0400 Improve 64->128 bit zero extension on PowerPC 2023-05-01 Michael Meissner gcc/ PR target/108958 * gcc/config/rs6000.md (zero_extendditi2): New insn. gcc/testsuite/ PR target/108958 * gcc.target/powerpc/zero-extend-di-ti.c: New test. Diff: --- gcc/config/rs6000/rs6000.md | 52 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0e1f4cb3868..7d6c94aee5b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -986,6 +986,58 @@ (set_attr "dot" "yes") (set_attr "length" "4,8")]) +(define_insn_and_split "zero_extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa") + (zero_extend:TI + (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa"))) + (clobber (match_scratch:DI 2 "=&X,X,X,X,wa"))] + "TARGET_POWERPC64 && TARGET_P9_VECTOR" + "@ + # + # + mtvsrdd %x0,0,%1 + lxvrdx %x0,%y1 + #" + "&& reload_completed + && (int_reg_operand (operands[0], TImode) + || (vsx_register_operand (operands[0], TImode) + && vsx_register_operand (operands[1], DImode)))" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 3) (const_int 0))] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + + /* If we are converting a VSX DImode to VSX TImode, we need to move the upper + 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi + instruction to swap the two 64-bit words, because can't rely on the bottom + 64-bits of the VSX register being 0. Instead we create a 0 and do the + xxpermdi operation to combine the two registers. */ + if (vsx_register_operand (dest, TImode) + && vsx_register_operand (src, DImode)) + { + rtx tmp = operands[2]; + emit_move_insn (tmp, const0_rtx); + + rtx hi = tmp; + rtx lo = src; + if (!BYTES_BIG_ENDIAN) + std::swap (hi, lo); + + rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest)); + emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo)); + DONE; + } + + /* If we are zero extending to a GPR register either from a GPR register, + a VSX register or from memory, do the zero extend operation to the + lower DI register, and set the upper DI register to 0. */ + operands[2] = gen_lowpart (DImode, dest); + operands[3] = gen_highpart (DImode, dest); +} + [(set_attr "type" "*,load,vecexts,vecload,vecperm") + (set_attr "isa" "*,*,p9v,p10,*") + (set_attr "length" "8,8,*,*,8")]) (define_insn "extendqi2" [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")