From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 1E2023858D1E; Mon, 1 May 2023 20:20:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1E2023858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682972407; bh=fJA3df1Xf76Ep5dPt6mWI+BIxqHSkpswEo7M2sCei/s=; h=From:To:Subject:Date:From; b=mmQELZ9NW2s6BHuyugrnvWS5O6pZYX7mSRButYsXXRm/EYhPhhdwNIcZwutmz84kX snl5Q+0vTWgViQRCtuiSBRR873ngwGTntpLJsr28IaVGDX9lLn5SQ7C4eAmYyZKc3T v7ViUsjuI+IeWlBkaT8eJCTuoe5WLtHGRYC8G5fY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work120)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work120 X-Git-Oldrev: 386950384507b51861dc2c504768b643138218d6 X-Git-Newrev: 08186cfb5f1671eba5cf909e72946171825ec759 Message-Id: <20230501202007.1E2023858D1E@sourceware.org> Date: Mon, 1 May 2023 20:20:07 +0000 (GMT) List-Id: https://gcc.gnu.org/g:08186cfb5f1671eba5cf909e72946171825ec759 commit 08186cfb5f1671eba5cf909e72946171825ec759 Author: Michael Meissner Date: Mon May 1 16:20:03 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/rs6000.md | 52 --------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7d6c94aee5b..0e1f4cb3868 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -986,58 +986,6 @@ (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn_and_split "zero_extendditi2" - [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa") - (zero_extend:TI - (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa"))) - (clobber (match_scratch:DI 2 "=&X,X,X,X,wa"))] - "TARGET_POWERPC64 && TARGET_P9_VECTOR" - "@ - # - # - mtvsrdd %x0,0,%1 - lxvrdx %x0,%y1 - #" - "&& reload_completed - && (int_reg_operand (operands[0], TImode) - || (vsx_register_operand (operands[0], TImode) - && vsx_register_operand (operands[1], DImode)))" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 3) (const_int 0))] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - - /* If we are converting a VSX DImode to VSX TImode, we need to move the upper - 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi - instruction to swap the two 64-bit words, because can't rely on the bottom - 64-bits of the VSX register being 0. Instead we create a 0 and do the - xxpermdi operation to combine the two registers. */ - if (vsx_register_operand (dest, TImode) - && vsx_register_operand (src, DImode)) - { - rtx tmp = operands[2]; - emit_move_insn (tmp, const0_rtx); - - rtx hi = tmp; - rtx lo = src; - if (!BYTES_BIG_ENDIAN) - std::swap (hi, lo); - - rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest)); - emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo)); - DONE; - } - - /* If we are zero extending to a GPR register either from a GPR register, - a VSX register or from memory, do the zero extend operation to the - lower DI register, and set the upper DI register to 0. */ - operands[2] = gen_lowpart (DImode, dest); - operands[3] = gen_highpart (DImode, dest); -} - [(set_attr "type" "*,load,vecexts,vecload,vecperm") - (set_attr "isa" "*,*,p9v,p10,*") - (set_attr "length" "8,8,*,*,8")]) (define_insn "extendqi2" [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")