From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3BB0C3858D1E; Mon, 1 May 2023 21:46:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3BB0C3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682977606; bh=BvNy7Ph5d0a0W4Qbala75Kv3uK6/lYSL1mn1XxnpOuA=; h=From:To:Subject:Date:From; b=uJr/58h3csTraclfOokrhIu69nwwCQnxA6Yax7WTgj4Ryfa5PLHKok0BaYIJOUIkh lqvR9QjKPHTjpU8eqGtcmvf+ADqH542nShxZIM8RvmP5uyZwwbr4GFa1STaSuWiqy2 Xc5oL4gDsxMcTE5Cn9T8X6kvKJVdCL0O8F35MNwg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work120)] Allow variable element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work120 X-Git-Oldrev: 3ab75878e878eac0765d31149682221345b9817e X-Git-Newrev: cf6c9e6421d08e310767571d97c8b3967a7ba0c2 Message-Id: <20230501214646.3BB0C3858D1E@sourceware.org> Date: Mon, 1 May 2023 21:46:46 +0000 (GMT) List-Id: https://gcc.gnu.org/g:cf6c9e6421d08e310767571d97c8b3967a7ba0c2 commit cf6c9e6421d08e310767571d97c8b3967a7ba0c2 Author: Michael Meissner Date: Mon May 1 17:46:24 2023 -0400 Allow variable element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a variable element number to be loaded into vector registers directly. 2023-05-1 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load): Allow vector registers to be loaded. Diff: --- gcc/config/rs6000/vsx.md | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 9c3e07fbfce..65bec8e1d5f 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4159,23 +4159,25 @@ } [(set_attr "isa" "p9v,*")]) -;; Variable V16QI/V8HI/V4SI extract from memory +;; Variable V16QI/V8HI/V4SI extract from memory. (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,wa") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,")]) ;; ISA 3.1 extract (define_expand "vextractl"