From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A81F53858D1E; Mon, 1 May 2023 22:38:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A81F53858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682980685; bh=qxhyTVUnL/Gg9BF2nkWO3PGL00RJ2WIaZBRf480vnrI=; h=From:To:Subject:Date:From; b=SYfEgOpISJm6JONdA8ktMgUoJNEuo95KFrs0haqcUsIewBfa4SVP49y76cjkkE4V4 O9FydTaV5nQ1jSXrDm9Xs9bBs7Bc4sNRgjqGJMYA/Dgdam5aUB8zYWzt0kQtzHhusu uZb2s5n8QSVIgcfDxv1HEv8zZwviTZR+iy9rQpEg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work120)] Optimize variable element vec_extract to be converted to floating point X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work120 X-Git-Oldrev: 6a16277a48961b2e80c012a4068c3940d4d9ec04 X-Git-Newrev: 9c3aeec2078ca25fc3986912e2aa459c92dacd6e Message-Id: <20230501223805.A81F53858D1E@sourceware.org> Date: Mon, 1 May 2023 22:38:05 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9c3aeec2078ca25fc3986912e2aa459c92dacd6e commit 9c3aeec2078ca25fc3986912e2aa459c92dacd6e Author: Michael Meissner Date: Mon May 1 18:37:48 2023 -0400 Optimize variable element vec_extract to be converted to floating point This patch optimizes vec_extract with a variable element number of the following types to be converted to floating point by loading the value directly to the vector register, and then doing the conversion instead of loading the value to a GPR and then doing a direct move: vector int vector unsigned int vector unsigned short vector unsigned char 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_): New * insn. * vsx_extract__var_load_to_uns: New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-int-6.c: New file. * gcc.target/powerpc/vec-extract-mem-int_7.c: New file. Diff: --- gcc/config/rs6000/vsx.md | 52 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-{int-6}.c | 0 .../gcc.target/powerpc/vec-extract-mem-{int-7}.c | 0 3 files changed, 52 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 47e5a9c4709..410183dde93 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4295,6 +4295,58 @@ } [(set_attr "type" "load")]) +;; Fold extracting a V4SI element with a variable element with either sign or +;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID. +(define_insn_and_split "*vsx_extract_v4si_var_load_to_" + [(set (match_operand:SFDF 0 "register_operand" "=wa") + (any_float:SFDF + (unspec:SI + [(match_operand:V4SI 1 "memory_operand" "Q") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b")) + (clobber (match_scratch:DI 4 "=wa"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 4) + (:DI (match_dup 5))) + (set (match_dup 0) + (float:SFDF (match_dup 4)))] +{ + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + +;; Fold extracting a V8HI/V16QI element with a variable element with zero +;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID +(define_insn_and_split "*vsx_extract__var_load_to_uns" + [(set (match_operand:SFDF 0 "register_operand" "=wa") + (unsigned_float:SFDF + (unspec: + [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b")) + (clobber (match_scratch:DI 4 "=v"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_P9_VECTOR" + "#" + "&& reload_completed" + [(set (match_dup 4) + (zero_extend:DI (match_dup 5))) + (set (match_dup 0) + (float:SFDF (match_dup 4)))] +{ + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-{int-6}.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-{int-6}.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-{int-7}.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-{int-7}.c new file mode 100644 index 00000000000..e69de29bb2d