From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id C6FE43858D1E; Tue, 2 May 2023 15:35:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C6FE43858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683041731; bh=wnpKB9CrYgrslf2F9zVmyy7y/2hhJY+JjgcClHGS8FQ=; h=From:To:Subject:Date:From; b=SKwEH8W7RSZ7fWQz+nvsLFT9ESv34b3UOeNL63WOAtSGifeicAUa741p8tvvSr1kf A14xO4CqlYEo2YSXTKKDRwe1xZuhWcqMLTMJKqjIUmwSCUzdbxFyYfec7USK811y+1 Ceck9R7UtUZom/AJiNM+KlIxrsTwNOkyp34vdWok= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-395] RISC-V: ICE for vlmul_ext_v intrinsic API X-Act-Checkin: gcc X-Git-Author: Yanzhang Wang X-Git-Refname: refs/heads/master X-Git-Oldrev: 87c347c2897537a6aa391efbfc5ed00c625434fe X-Git-Newrev: 1adb1a653d6739589b12337c974c7e741cfb187c Message-Id: <20230502153531.C6FE43858D1E@sourceware.org> Date: Tue, 2 May 2023 15:35:31 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1adb1a653d6739589b12337c974c7e741cfb187c commit r14-395-g1adb1a653d6739589b12337c974c7e741cfb187c Author: Yanzhang Wang Date: Wed Apr 26 21:06:02 2023 +0800 RISC-V: ICE for vlmul_ext_v intrinsic API PR target/109617 gcc/ChangeLog: * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Pan Li Signed-off-by: Yanzhang Wang Diff: --- gcc/config/riscv/vector-iterators.md | 3 ++- gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a8e856161d3..033659930d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -189,6 +189,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -220,7 +221,7 @@ (define_mode_iterator VLMULEXT32 [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128") - (VNx1HI "TARGET_MIN_VLEN < 128") + (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VLMULEXT64 [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c new file mode 100644 index 00000000000..501d98c5897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include + +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { + return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); +} + +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { + return __riscv_vlmul_ext_v_i64m2_i64m8(op1); +} + +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */