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From: Patrick O'Neill <poneill@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-400] RISC-V: Enforce subword atomic LR/SC SEQ_CST Date: Tue, 2 May 2023 20:10:18 +0000 (GMT) [thread overview] Message-ID: <20230502201018.F15403858410@sourceware.org> (raw) https://gcc.gnu.org/g:4990cf84c460f064d6281d0813f20b0ef20c7448 commit r14-400-g4990cf84c460f064d6281d0813f20b0ef20c7448 Author: Patrick O'Neill <patrick@rivosinc.com> Date: Fri Apr 21 13:11:35 2023 -0700 RISC-V: Enforce subword atomic LR/SC SEQ_CST Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Diff: --- gcc/config/riscv/sync.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 19274528262..0c83ef04607 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -109,7 +109,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "<insn>\t%5, %0, %2\;" "and\t%5, %5, %3\;" "and\t%6, %0, %4\;" @@ -173,7 +173,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%5, %0, %2\;" "not\t%5, %5\;" "and\t%5, %5, %3\;" @@ -278,7 +278,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%4, %0, %3\;" "or\t%4, %4, %2\;" "sc.w.rl\t%4, %4, %1\;" @@ -443,7 +443,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%6, %0, %4\;" "bne\t%6, %z2, 1f\;" "and\t%6, %0, %5\;"
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