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From: Patrick O'Neill <poneill@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-401] RISC-V: Enforce atomic compare_exchange SEQ_CST Date: Tue, 2 May 2023 20:10:24 +0000 (GMT) [thread overview] Message-ID: <20230502201024.1BC9B3858002@sourceware.org> (raw) https://gcc.gnu.org/g:d199d2e56da2379004e7e0457150409c0c99d3e6 commit r14-401-gd199d2e56da2379004e7e0457150409c0c99d3e6 Author: Patrick O'Neill <patrick@rivosinc.com> Date: Wed Apr 5 09:46:37 2023 -0700 RISC-V: Enforce atomic compare_exchange SEQ_CST This patch enforces SEQ_CST for atomic compare_exchange ops. Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (atomic_cas_value_strong<mode>): Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Diff: --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 0c83ef04607..5620d6ffa58 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -297,9 +297,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr.<amo>.aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc.<amo>.rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap<mode>" [(match_operand:SI 0 "register_operand" "") ;; bool output
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