From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 37EEE385840F; Fri, 12 May 2023 21:33:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 37EEE385840F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683927227; bh=iEHUnylTWJt/+EG63oZ+NscHoDekSETwEYvxWAzjhq0=; h=From:To:Subject:Date:From; b=paUnz9KqzlyXKTi8vFBdrVOeioXRecrGP0RLi+NJdMbVnNdC6BpXa6GWp5//4mvRV u8rzqSWd9Ouz8xkOHuLO0fZYGrfbJm4XwxVUFGyzxV8mqrVpAYySBmm86i3hwxY8MY FJQ4vMfZYwFvzxeMMpXCo898RnAcFmcC/e75Mdkk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work121)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work121 X-Git-Oldrev: a530f2a62b6175cba3e6f3fcde33afe58fd331a6 X-Git-Newrev: 27ef909046b398f55b08c0ba93b3ea6984da8d83 Message-Id: <20230512213347.37EEE385840F@sourceware.org> Date: Fri, 12 May 2023 21:33:47 +0000 (GMT) List-Id: https://gcc.gnu.org/g:27ef909046b398f55b08c0ba93b3ea6984da8d83 commit 27ef909046b398f55b08c0ba93b3ea6984da8d83 Author: Michael Meissner Date: Fri May 12 17:33:43 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 178 +++++++++------------ .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 ---- .../gcc.target/powerpc/vec-extract-mem-float-2.c | 22 --- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 31 ++++ .../gcc.target/powerpc/vec-extract-mem-short-3.c | 19 +++ 5 files changed, 129 insertions(+), 150 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2809dc6b011..fe19b35dbbe 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,12 +223,6 @@ (V8HI "v") (V4SI "wa")]) -;; Mode attribute to give the isa constraint for accessing Altivec registers -;; with vector extract and insert operations. -(define_mode_attr VSX_EX_ISA [(V16QI "p9v") - (V8HI "p9v") - (V4SI "p8v")]) - ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3555,33 +3549,12 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory with constant element number. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -;; 8: GPR 0 any normal address no -;; 9: GPR 0-3 any offsettable address no -;; 10: GPR 0-3 any single register yes (define_insn_and_split "*vsx_extract_v4sf_load" - [(set (match_operand:SF 0 "register_operand" - "=f, f, f, v, v, v, v, - r, r, r") + [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o, - m, o, Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "O, n, n, O, n, O, n, - O, n, n")]))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X, - X, X, &b"))] + (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) + (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" "&& reload_completed" @@ -3590,47 +3563,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload, - load, load, load") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v, - *, *, *")]) - -;; V4SF extract from memory with constant element number and convert to DFmode. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" - "=f, f, f, v, v, v, v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "=X, X, &b, X, &b, X, X")])))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v")]) + [(set_attr "type" "fpload,fpload,fpload,load") + (set_attr "length" "8") + (set_attr "isa" "*,p7v,p9v,*")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" @@ -3652,7 +3587,7 @@ ;; Variable V4SF extract from memory (define_insn_and_split "*vsx_extract_v4sf_var_load" - [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,r") + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r") (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q") (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) @@ -3667,25 +3602,6 @@ } [(set_attr "type" "fpload,load")]) -;; V4SF extract from memory with variable element number and convert to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload")]) - ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") @@ -4052,25 +3968,89 @@ } [(set_attr "isa" "p9v,*")]) -;; Variable V16QI/V8HI/V4SI extract from memory. +;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r,wa") + [(set (match_operand: 0 "gpc_reg_operand" "=r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b,&b"))] + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); +} + [(set_attr "type" "load")]) + +;; Variable V4SI extract from memory with sign or zero conversion to DImode. +(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") + (any_extend:DI + (unspec:SI + [(match_operand:V4SI 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:DI (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "load,fpload")]) + +;; Variable V8HI/V16QI extract from memory with zero conversion to either +;; SImode or DImode. +(define_insn_and_split "*vsx_extract__var_load_to_u" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,wa") + (zero_extend:GPR + (unspec: + [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:GPR (match_dup 4)))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], - mode); + mode); } [(set_attr "type" "load,fpload") - (set_attr "isa" "*,")]) + (set_attr "isa" "*,p9v")]) + +;; Variable V8HI extract from memory with sign conversion to either +;; SImode or DImode. +(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (sign_extend:GPR + (unspec:HI + [(match_operand:V8HI 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (sign_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + HImode); +} + [(set_attr "type" "load")]) ;; ISA 3.1 extract (define_expand "vextractl" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index 4670e261ba8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include - -void -extract_v4sf_gpr_0 (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -void -extract_v4sf_gpr_1 (vector float *p, float *q) -{ - float x = vec_extract (*p, 1); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c deleted file mode 100644 index 2561aa930b6..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c +++ /dev/null @@ -1,22 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include -#include - -void -extract_v4sf_gpr_n (vector float *p, float *q, size_t n) -{ - float x = vec_extract (*p, n); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c new file mode 100644 index 00000000000..f6b027db3bc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Test to verify that the vec_extract with variable element numbers can load + SImode and fold both zero and sign extension into the load. Both uses + generate a rldicl to clear the bits in the variable element number, but this + test verifies that there is no rldicl after the lwzx to do the zero + extension. */ + +#include +#include + +long long +extract_sign_v4si_var (vector int *p, size_t n) +{ + return vec_extract (*p, n); /* lwax, no extsw. */ +} + +unsigned long long +extract_uns_v4si_var (vector unsigned int *p, size_t n) +{ + return vec_extract (*p, n); /* lwzx, no extra rldicl. */ +} + +/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ +/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ +/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c new file mode 100644 index 00000000000..a1d3947fabb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Test to verify that the vec_extract with variable element numbers can load + HImode and fold sign extension into the load. */ + +#include +#include + +long long +extract_sign_v8hi_var (vector short *p, size_t n) +{ + return vec_extract (*p, n); /* lwax, no extsw. */ +} + +/* { dg-final { scan-assembler {\mlhax\M} } } */ +/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */ +/* { dg-final { scan-assembler-not {\mextsh\M} } } */