From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 6B0573858CDB; Fri, 12 May 2023 22:54:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6B0573858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683932095; bh=fio+TK7FcGbLKmheQu9ENyD6s/gEo6Dr74JkEzOotSw=; h=From:To:Subject:Date:From; b=mw1QerF2z3+5V1k6LiNOaRSWP2MZg0oJ7NU5IY/IiHmvMNG59JI2UZrxiKmRhxMfp SXoTLOHv72pZS4aI3bAw7XQBFzg1pMp34f3FxhdilVHd7jqw9KbADExRtC5AFbK2I9 ctu2X3tFdx0JXEJRDpIeiiv8m46RUafgeDo99V9E= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work121)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work121 X-Git-Oldrev: 786294305a7c3bcd8e1727bf301b9ac7c6e41056 X-Git-Newrev: 10ad543da83a1f4819fe431c0e8a5ae5d03b6034 Message-Id: <20230512225455.6B0573858CDB@sourceware.org> Date: Fri, 12 May 2023 22:54:55 +0000 (GMT) List-Id: https://gcc.gnu.org/g:10ad543da83a1f4819fe431c0e8a5ae5d03b6034 commit 10ad543da83a1f4819fe431c0e8a5ae5d03b6034 Author: Michael Meissner Date: Fri May 12 18:54:51 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 73 +++------------------- .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 --------- .../gcc.target/powerpc/vec-extract-mem-float-2.c | 0 3 files changed, 7 insertions(+), 95 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 1686c7f335b..2d513784a90 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3549,33 +3549,12 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory with constant element number. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -;; 8: GPR 0 any normal address no -;; 9: GPR 0-3 any offsettable address no -;; 10: GPR 0-3 any single register yes (define_insn_and_split "*vsx_extract_v4sf_load" - [(set (match_operand:SF 0 "register_operand" - "=f, f, f, v, v, v, v, - r, r, r") + [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o, - m, o, Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "O, n, n, O, n, O, n, - O, n, n")]))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X, - X, X, &b"))] + (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) + (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" "&& reload_completed" @@ -3584,47 +3563,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload, - load, load, load") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v, - *, *, *")]) - -;; V4SF extract from memory with constant element number and convert to DFmode. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" - "=f, f, f, v, v, v, v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "=X, X, &b, X, &b, X, X")])))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v")]) + [(set_attr "type" "fpload,fpload,fpload,load") + (set_attr "length" "8") + (set_attr "isa" "*,p7v,p9v,*")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index 4670e261ba8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include - -void -extract_v4sf_gpr_0 (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -void -extract_v4sf_gpr_1 (vector float *p, float *q) -{ - float x = vec_extract (*p, 1); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c new file mode 100644 index 00000000000..e69de29bb2d