[gcc r14-1003] RISC-V: Remove masking third operand of rotate instructions

[gcc r14-1003] RISC-V: Remove masking third operand of rotate instructions

[Jeff Law]

https://gcc.gnu.org/g:259b4b7d349dd3fd560144bd4617f526458b45dc

commit r14-1003-g259b4b7d349dd3fd560144bd4617f526458b45dc
Author: Joern Rennecke <joern.rennecke@embecosm.com>
Date:   Fri May 19 16:18:42 2023 -0600

    RISC-V: Remove masking third operand of rotate instructions
    
    Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
    part of the subject.
    
    2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>
    
    gcc/ChangeLog:
            * config/riscv/constraints.md (DsS, DsD): Restore agreement
            with shiftm1 mode attribute.

Diff:
---
 gcc/config/riscv/constraints.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c448e6b37e9..44525b2da49 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -65,13 +65,13 @@
   "@internal
    31 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 31")))
+       (match_test "(ival & 31) == 31")))
 
 (define_constraint "DsD"
   "@internal
    63 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 63")))
+       (match_test "(ival & 63) == 63")))
 
 (define_constraint "DbS"
   "@internal"