From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id 8D4C33858423; Tue, 23 May 2023 04:01:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8D4C33858423 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684814510; bh=cTeIQ/IjKIsE9UDwf4fIf9xbubSWmombmlnp9Qkf/X0=; h=From:To:Subject:Date:From; b=w3OMKlEk2FccXjjkcHYtTGtWwYnRweDqAJdlNFK/696/0WtSBxW8NER09Q+wTxQlu iCoHTKDOuJgA8DZiqlz4hQ/78zF7UKFP/cIJWklOX7nWBApjjLX+6dQHe8yiwUgX59 W7k4SXbs5KLbnaobrpi4WsszQnU90FVUCRZ9iFQM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract* X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: e40d144e5f8ccd836eb04a809eb21ae6eaa42b11 X-Git-Newrev: 4ab0b0acabefaf115adaeac3b77c068c4dd1b17c Message-Id: <20230523040150.8D4C33858423@sourceware.org> Date: Tue, 23 May 2023 04:01:50 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4ab0b0acabefaf115adaeac3b77c068c4dd1b17c commit 4ab0b0acabefaf115adaeac3b77c068c4dd1b17c Author: Alexandre Oliva Date: Mon May 22 17:26:40 2023 -0300 [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract* Codegen changes caused add instruction count mismatches on ppc-*-linux-gnu and other 32-bit ppc targets. At some point the expected counts were adjusted for lp64, but ilp32 differences remained, and published test results confirm it. for gcc/testsuite/ChangeLog * gcc.target/powerpc/fold-vec-extract-char.p7.c: Adjust addi counts for ilp32. * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. TN: W519-006 Diff: --- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c | 3 ++- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +- 8 files changed, 9 insertions(+), 8 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c index 29a8aa84db2..c6647431d09 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c @@ -11,7 +11,8 @@ /* one extsb (extend sign-bit) instruction generated for each test against unsigned types */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 9 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target { ilp32 } } } } */ /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ /* -m32 target uses rlwinm in place of rldicl. */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c index 3cae644b90b..db325efbb07 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c @@ -14,7 +14,7 @@ /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ /* -m32 target has an 'add' in place of one of the 'addi'. */ /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } } } */ /* -m32 target has a rlwinm in place of a rldic . */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c index 59a4979457d..42ec69475fd 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c @@ -13,7 +13,7 @@ /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ /* -m32 as an add in place of an addi. */ /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */ /* -m32 uses rlwinm in place of rldic */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c index 4b1d75ee26d..68eeeede4b3 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c @@ -26,7 +26,7 @@ /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c index 3729a1646e9..e8130693ee9 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c @@ -11,7 +11,7 @@ /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c index 75eaf25943b..d1e3b62373f 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c @@ -30,7 +30,7 @@ /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c index a495d9f3928..ec3b78bac5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c @@ -11,7 +11,7 @@ /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */ /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c index 0ddecb4e4b5..00685aca136 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c @@ -32,7 +32,7 @@ /* add and rlwinm instructions only on the variable tests. */ /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */