[gcc r14-1141] xtensa: Merge '*addx' and '*subx' insn patterns into one

[gcc r14-1141] xtensa: Merge '*addx' and '*subx' insn patterns into one

[Max Filippov]

https://gcc.gnu.org/g:8a20b4bc50bdc8d61610974d60d5851f3fd8b70f

commit r14-1141-g8a20b4bc50bdc8d61610974d60d5851f3fd8b70f
Author: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date:   Mon May 22 16:04:37 2023 +0900

    xtensa: Merge '*addx' and '*subx' insn patterns into one
    
    By making use of the 'addsub_operator' added in the last patch.
    
    gcc/ChangeLog:
    
            * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
            and change to also accept '*subx' pattern.
            (*subx): Remove.

Diff:
---
 gcc/config/xtensa/xtensa.md | 31 +++++++++++++------------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index c75fde1023a..6c1d8ee8f81 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -170,15 +170,24 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"2,2,3,3,3")])
 
-(define_insn "*addx"
+(define_insn "*addsubx"
   [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
+	(match_operator:SI 4 "addsub_operator"
+		[(ashift:SI (match_operand:SI 1 "register_operand" "r")
 			    (match_operand:SI 3 "addsubx_operand" "i"))
-		 (match_operand:SI 2 "register_operand" "r")))]
+		 (match_operand:SI 2 "register_operand" "r")]))]
   "TARGET_ADDX"
 {
   operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-  return "addx%3\t%0, %1, %2";
+  switch (GET_CODE (operands[4]))
+    {
+    case PLUS:
+      return "addx%3\t%0, %1, %2";
+    case MINUS:
+      return "subx%3\t%0, %1, %2";
+    default:
+      gcc_unreachable ();
+    }
 }
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
@@ -207,20 +216,6 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-(define_insn "*subx"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-			     (match_operand:SI 3 "addsubx_operand" "i"))
-		  (match_operand:SI 2 "register_operand" "r")))]
-  "TARGET_ADDX"
-{
-  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-  return "subx%3\t%0, %1, %2";
-}
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"3")])
-
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(minus:SF (match_operand:SF 1 "register_operand" "f")