From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 7984B3858D32; Thu, 25 May 2023 14:51:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7984B3858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685026303; bh=oY9zpZQYWTJI0bByyrXiOOAlh2ACw2bxhDndElKrVMU=; h=From:To:Subject:Date:From; b=piT7bwPELGqBDoL7Xa6WZ8jSc6uDEALvJAp+Qg1WzPNfJttzTAV3kp6oZbndWZxAd HuZWgSiGbvPF1Dcg9g0xysGIvc/IYC09lO0migi0xl+Hu3CxKAJ7oOGxinHS13SCHR fJI/4w1ZRga5iD63WpjMz3z2Ubdfrz1lGvdJEEaU= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-1243] arm: merge MVE_5 and MVE_6 iterators X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/heads/master X-Git-Oldrev: f574e2dfae79055f16d0c63cc12df24815d8ead6 X-Git-Newrev: 19fc92d8a99ed60ee3b652727f222ea656550e55 Message-Id: <20230525145143.7984B3858D32@sourceware.org> Date: Thu, 25 May 2023 14:51:43 +0000 (GMT) List-Id: https://gcc.gnu.org/g:19fc92d8a99ed60ee3b652727f222ea656550e55 commit r14-1243-g19fc92d8a99ed60ee3b652727f222ea656550e55 Author: Christophe Lyon Date: Thu May 25 12:19:52 2023 +0000 arm: merge MVE_5 and MVE_6 iterators MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 with MVE_5 everywhere in mve.md and removes MVE_6 from iterators.md. 2023-05-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_6): Remove. * config/arm/mve.md: Replace MVE_6 with MVE_5. Diff: --- gcc/config/arm/iterators.md | 1 - gcc/config/arm/mve.md | 68 ++++++++++++++++++++++----------------------- 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 597c1dae640..9e77af55d60 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -272,7 +272,6 @@ (define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) -(define_mode_iterator MVE_6 [V8HI V4SI]) (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI]) (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI]) (define_mode_iterator MVE_V8HF [V8HF]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9e3570c5264..74909ce47e1 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -3732,9 +3732,9 @@ ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] ;; (define_insn "mve_vldrhq_gather_offset_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") - (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") - (match_operand:MVE_6 2 "s_register_operand" "w")] + [(set (match_operand:MVE_5 0 "s_register_operand" "=&w") + (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_5 2 "s_register_operand" "w")] VLDRHGOQ)) ] "TARGET_HAVE_MVE" @@ -3755,9 +3755,9 @@ ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] ;; (define_insn "mve_vldrhq_gather_offset_z_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") - (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") - (match_operand:MVE_6 2 "s_register_operand" "w") + [(set (match_operand:MVE_5 0 "s_register_operand" "=&w") + (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up") ]VLDRHGOQ)) ] @@ -3780,9 +3780,9 @@ ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] ;; (define_insn "mve_vldrhq_gather_shifted_offset_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") - (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") - (match_operand:MVE_6 2 "s_register_operand" "w")] + [(set (match_operand:MVE_5 0 "s_register_operand" "=&w") + (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_5 2 "s_register_operand" "w")] VLDRHGSOQ)) ] "TARGET_HAVE_MVE" @@ -3803,9 +3803,9 @@ ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] ;; (define_insn "mve_vldrhq_gather_shifted_offset_z_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") - (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") - (match_operand:MVE_6 2 "s_register_operand" "w") + [(set (match_operand:MVE_5 0 "s_register_operand" "=&w") + (unspec:MVE_5 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up") ]VLDRHGSOQ)) ] @@ -3828,8 +3828,8 @@ ;; [vldrhq_s, vldrhq_u] ;; (define_insn "mve_vldrhq_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=w") - (unspec:MVE_6 [(match_operand: 1 "mve_memory_operand" "Ux")] + [(set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "mve_memory_operand" "Ux")] VLDRHQ)) ] "TARGET_HAVE_MVE" @@ -3870,8 +3870,8 @@ ;; [vldrhq_z_s vldrhq_z_u] ;; (define_insn "mve_vldrhq_z_" - [(set (match_operand:MVE_6 0 "s_register_operand" "=w") - (unspec:MVE_6 [(match_operand: 1 "mve_memory_operand" "Ux") + [(set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "mve_memory_operand" "Ux") (match_operand: 2 "vpr_register_operand" "Up")] VLDRHQ)) ] @@ -4449,7 +4449,7 @@ (define_insn "mve_vstrhq_p_" [(set (match_operand: 0 "mve_memory_operand" "=Ux") (unspec: - [(match_operand:MVE_6 1 "s_register_operand" "w") + [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand: 2 "vpr_register_operand" "Up") (match_dup 0)] VSTRHQ)) @@ -4470,8 +4470,8 @@ ;; (define_expand "mve_vstrhq_scatter_offset_p_" [(match_operand: 0 "mve_scatter_memory") - (match_operand:MVE_6 1 "s_register_operand") - (match_operand:MVE_6 2 "s_register_operand") + (match_operand:MVE_5 1 "s_register_operand") + (match_operand:MVE_5 2 "s_register_operand") (match_operand: 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSOQ)] "TARGET_HAVE_MVE" @@ -4489,8 +4489,8 @@ [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:SI 0 "register_operand" "r") - (match_operand:MVE_6 1 "s_register_operand" "w") - (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] VSTRHSOQ))] "TARGET_HAVE_MVE" @@ -4502,8 +4502,8 @@ ;; (define_expand "mve_vstrhq_scatter_offset_" [(match_operand: 0 "mve_scatter_memory") - (match_operand:MVE_6 1 "s_register_operand") - (match_operand:MVE_6 2 "s_register_operand") + (match_operand:MVE_5 1 "s_register_operand") + (match_operand:MVE_5 2 "s_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSOQ)] "TARGET_HAVE_MVE" { @@ -4518,8 +4518,8 @@ [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:SI 0 "register_operand" "r") - (match_operand:MVE_6 1 "s_register_operand" "w") - (match_operand:MVE_6 2 "s_register_operand" "w")] + (match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] VSTRHSOQ))] "TARGET_HAVE_MVE" "vstrh.\t%q2, [%0, %q1]" @@ -4530,8 +4530,8 @@ ;; (define_expand "mve_vstrhq_scatter_shifted_offset_p_" [(match_operand: 0 "mve_scatter_memory") - (match_operand:MVE_6 1 "s_register_operand") - (match_operand:MVE_6 2 "s_register_operand") + (match_operand:MVE_5 1 "s_register_operand") + (match_operand:MVE_5 2 "s_register_operand") (match_operand: 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] "TARGET_HAVE_MVE" @@ -4549,8 +4549,8 @@ [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:SI 0 "register_operand" "r") - (match_operand:MVE_6 1 "s_register_operand" "w") - (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] VSTRHSSOQ))] "TARGET_HAVE_MVE" @@ -4562,8 +4562,8 @@ ;; (define_expand "mve_vstrhq_scatter_shifted_offset_" [(match_operand: 0 "mve_scatter_memory") - (match_operand:MVE_6 1 "s_register_operand") - (match_operand:MVE_6 2 "s_register_operand") + (match_operand:MVE_5 1 "s_register_operand") + (match_operand:MVE_5 2 "s_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] "TARGET_HAVE_MVE" { @@ -4579,8 +4579,8 @@ [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:SI 0 "register_operand" "r") - (match_operand:MVE_6 1 "s_register_operand" "w") - (match_operand:MVE_6 2 "s_register_operand" "w")] + (match_operand:MVE_5 1 "s_register_operand" "w") + (match_operand:MVE_5 2 "s_register_operand" "w")] VSTRHSSOQ))] "TARGET_HAVE_MVE" "vstrh.\t%q2, [%0, %q1, uxtw #1]" @@ -4591,7 +4591,7 @@ ;; (define_insn "mve_vstrhq_" [(set (match_operand: 0 "mve_memory_operand" "=Ux") - (unspec: [(match_operand:MVE_6 1 "s_register_operand" "w")] + (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w")] VSTRHQ)) ] "TARGET_HAVE_MVE"