[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Refactor the or pattern to switch cases

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Refactor the or pattern to switch cases

[Jeff Law]

https://gcc.gnu.org/g:9160e78714477b8c92bac8489f73fc4341d5c2c9

commit 9160e78714477b8c92bac8489f73fc4341d5c2c9
Author: Pan Li <pan2.li@intel.com>
Date:   Sun May 14 16:15:11 2023 +0800

    RISC-V: Refactor the or pattern to switch cases
    
    This patch refactor the pattern A or B or C or D, to the switch case for
    easy add/remove new types, as well as human reading friendly.
    
    Before this patch:
    return A || B || C || D;
    
    After this patch:
    switch (type)
      {
        case A:
        case B:
        case C:
        case D:
          return true;
        default:
          return false;
      }
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-vector-builtins.cc (required_extensions_p):
            Refactor the or pattern to switch cases.

Diff:
---
 gcc/config/riscv/riscv-vector-builtins.cc | 37 ++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 4117897c6c9..0f56f29f7aa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type)
 static bool
 required_extensions_p (enum rvv_base_type type)
 {
-  return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index
-	 || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index
-	 || type == RVV_BASE_float_vector
-	 || type == RVV_BASE_double_trunc_float_vector
-	 || type == RVV_BASE_double_trunc_vector
-	 || type == RVV_BASE_widen_lmul1_vector
-	 || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret
-	 || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret
-	 || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4
-	 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16
-	 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64;
+  switch (type)
+    {
+      case RVV_BASE_eew8_index:
+      case RVV_BASE_eew16_index:
+      case RVV_BASE_eew32_index:
+      case RVV_BASE_eew64_index:
+      case RVV_BASE_float_vector:
+      case RVV_BASE_double_trunc_float_vector:
+      case RVV_BASE_double_trunc_vector:
+      case RVV_BASE_widen_lmul1_vector:
+      case RVV_BASE_eew8_interpret:
+      case RVV_BASE_eew16_interpret:
+      case RVV_BASE_eew32_interpret:
+      case RVV_BASE_eew64_interpret:
+      case RVV_BASE_vlmul_ext_x2:
+      case RVV_BASE_vlmul_ext_x4:
+      case RVV_BASE_vlmul_ext_x8:
+      case RVV_BASE_vlmul_ext_x16:
+      case RVV_BASE_vlmul_ext_x32:
+      case RVV_BASE_vlmul_ext_x64:
+	return true;
+      default:
+	return false;
+    }
+
+  gcc_unreachable ();
 }
 
 static uint64_t

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Refactor the or pattern to switch cases

[Jeff Law]

https://gcc.gnu.org/g:af53cce1b0171c09dd9e5f3960920190f13f9bbd

commit af53cce1b0171c09dd9e5f3960920190f13f9bbd
Author: Pan Li <pan2.li@intel.com>
Date:   Sun May 14 16:15:11 2023 +0800

    RISC-V: Refactor the or pattern to switch cases
    
    This patch refactor the pattern A or B or C or D, to the switch case for
    easy add/remove new types, as well as human reading friendly.
    
    Before this patch:
    return A || B || C || D;
    
    After this patch:
    switch (type)
      {
        case A:
        case B:
        case C:
        case D:
          return true;
        default:
          return false;
      }
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-vector-builtins.cc (required_extensions_p):
            Refactor the or pattern to switch cases.

Diff:
---
 gcc/config/riscv/riscv-vector-builtins.cc | 37 ++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 4117897c6c9..0f56f29f7aa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type)
 static bool
 required_extensions_p (enum rvv_base_type type)
 {
-  return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index
-	 || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index
-	 || type == RVV_BASE_float_vector
-	 || type == RVV_BASE_double_trunc_float_vector
-	 || type == RVV_BASE_double_trunc_vector
-	 || type == RVV_BASE_widen_lmul1_vector
-	 || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret
-	 || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret
-	 || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4
-	 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16
-	 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64;
+  switch (type)
+    {
+      case RVV_BASE_eew8_index:
+      case RVV_BASE_eew16_index:
+      case RVV_BASE_eew32_index:
+      case RVV_BASE_eew64_index:
+      case RVV_BASE_float_vector:
+      case RVV_BASE_double_trunc_float_vector:
+      case RVV_BASE_double_trunc_vector:
+      case RVV_BASE_widen_lmul1_vector:
+      case RVV_BASE_eew8_interpret:
+      case RVV_BASE_eew16_interpret:
+      case RVV_BASE_eew32_interpret:
+      case RVV_BASE_eew64_interpret:
+      case RVV_BASE_vlmul_ext_x2:
+      case RVV_BASE_vlmul_ext_x4:
+      case RVV_BASE_vlmul_ext_x8:
+      case RVV_BASE_vlmul_ext_x16:
+      case RVV_BASE_vlmul_ext_x32:
+      case RVV_BASE_vlmul_ext_x64:
+	return true;
+      default:
+	return false;
+    }
+
+  gcc_unreachable ();
 }
 
 static uint64_t