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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove trailing spaces on lines.
@ 2023-05-25 23:21 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-05-25 23:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7873002787a3bc14ce41963fa4c2e8f612efec02
commit 7873002787a3bc14ce41963fa4c2e8f612efec02
Author: Jin Ma <jinma@linux.alibaba.com>
Date: Wed May 17 15:44:03 2023 -0600
RISC-V: Remove trailing spaces on lines.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Remove
trailing spaces on lines.
* config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
* config/riscv/riscv.h (enum reg_class): Likewise.
* config/riscv/riscv.md: Likewise.
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 2 +-
gcc/config/riscv/riscv.cc | 6 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/riscv.md | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index fb2635eb559..c2ec74b9d92 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,7 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
-
+
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 93f3b07c1b5..235be758c03 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2166,8 +2166,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
}
return true;
}
- /* Expand
- (set (reg:QI target) (mem:QI (address)))
+ /* Expand
+ (set (reg:QI target) (mem:QI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
@@ -2182,7 +2182,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
temp_reg = gen_reg_rtx (word_mode);
zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
- emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
+ emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
zero_extend_p));
riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
return true;
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 29f2c07ce5d..807b0bccc18 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -578,7 +578,7 @@ enum reg_class
#define POLY_SMALL_OPERAND_P(POLY_VALUE) \
(POLY_VALUE.is_constant () ? \
SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
-
+
/* True if VALUE can be loaded into a register using LUI. */
#define LUI_OPERAND(VALUE) \
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e773bc748bf..124d8c95804 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -223,7 +223,7 @@
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
-
+
(and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
(const_string "yes")
@@ -259,7 +259,7 @@
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
-;; imul integer multiply
+;; imul integer multiply
;; idiv integer divide
;; move integer register move (addi rd, rs1, 0)
;; fmove floating point register move
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove trailing spaces on lines.
@ 2023-07-14 2:37 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:24a88da00c1faf7edcbe492f663e674390956a1d
commit 24a88da00c1faf7edcbe492f663e674390956a1d
Author: Jin Ma <jinma@linux.alibaba.com>
Date: Wed May 17 15:44:03 2023 -0600
RISC-V: Remove trailing spaces on lines.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Remove
trailing spaces on lines.
* config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
* config/riscv/riscv.h (enum reg_class): Likewise.
* config/riscv/riscv.md: Likewise.
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 2 +-
gcc/config/riscv/riscv.cc | 6 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/riscv.md | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 57a2a279ef5..5fc1ceb52d6 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,7 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
-
+
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f9f150d3605..8e3dd67632f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2166,8 +2166,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
}
return true;
}
- /* Expand
- (set (reg:QI target) (mem:QI (address)))
+ /* Expand
+ (set (reg:QI target) (mem:QI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
@@ -2182,7 +2182,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
temp_reg = gen_reg_rtx (word_mode);
zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
- emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
+ emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
zero_extend_p));
riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
return true;
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 29f2c07ce5d..807b0bccc18 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -578,7 +578,7 @@ enum reg_class
#define POLY_SMALL_OPERAND_P(POLY_VALUE) \
(POLY_VALUE.is_constant () ? \
SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
-
+
/* True if VALUE can be loaded into a register using LUI. */
#define LUI_OPERAND(VALUE) \
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e773bc748bf..124d8c95804 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -223,7 +223,7 @@
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
-
+
(and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
(const_string "yes")
@@ -259,7 +259,7 @@
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
-;; imul integer multiply
+;; imul integer multiply
;; idiv integer divide
;; move integer register move (addi rd, rs1, 0)
;; fmove floating point register move
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-05-25 23:21 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove trailing spaces on lines Jeff Law
2023-07-14 2:37 Jeff Law
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