From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 11F403882AC7; Mon, 5 Jun 2023 16:16:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 11F403882AC7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685981798; bh=yMZ6I2H3jYakJv2hHdFr3H5moodAFG/9YVNJBg1dsME=; h=From:To:Subject:Date:From; b=kgcCrqjCCKSugCcVIHZO1MhzFxALeFBEJ+x2n7Kj72gCOqU8U4AY9TWEWkAY16eOY zHABYTECJL8sJn3ZOBQlRAs3VqFFZC8qiNao57+aG35JAi8KOX5fobKGglu6EVdyCk lUujLvQWfez28N3zoM60Ms4qDjDi3bYtWhxLiFwA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfncvt.rod instruction X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 5c8f9376c9cebb5fba3f1aaa1ed7d5f2d8ce56ed X-Git-Newrev: da4570cf01a6a245b025e54ced0242771d1b3173 Message-Id: <20230605161638.11F403882AC7@sourceware.org> Date: Mon, 5 Jun 2023 16:16:38 +0000 (GMT) List-Id: https://gcc.gnu.org/g:da4570cf01a6a245b025e54ced0242771d1b3173 commit da4570cf01a6a245b025e54ced0242771d1b3173 Author: Juzhe-Zhong Date: Wed May 31 18:47:03 2023 +0800 RISC-V: Remove FRM for vfncvt.rod instruction Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li Diff: --- gcc/config/riscv/vector.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cd696da5d89..60f052bcec9 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7290,10 +7290,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)