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From: Jeff Law <law@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Move optimization patterns into autovec-opt.md Date: Mon, 5 Jun 2023 16:18:24 +0000 (GMT) [thread overview] Message-ID: <20230605161824.B2AB63883025@sourceware.org> (raw) https://gcc.gnu.org/g:9463f6c4043858afaa9de9937d1b65268e83cc7c commit 9463f6c4043858afaa9de9937d1b65268e83cc7c Author: Juzhe-Zhong <juzhe.zhong@rivai.ai> Date: Sun Jun 4 17:36:47 2023 +0800 RISC-V: Move optimization patterns into autovec-opt.md Move all optimization patterns into autovec-opt.md to make organization easier maintain. gcc/ChangeLog: * config/riscv/autovec-opt.md (*<optab>not<mode>): Move to autovec-opt.md. (*n<optab><mode>): Ditto. * config/riscv/autovec.md (*<optab>not<mode>): Ditto. (*n<optab><mode>): Ditto. * config/riscv/vector.md: Ditto. Diff: --- gcc/config/riscv/autovec-opt.md | 92 +++++++++++++++++++++++++++++++++++++++++ gcc/config/riscv/autovec.md | 52 ----------------------- gcc/config/riscv/vector.md | 39 ----------------- 3 files changed, 92 insertions(+), 91 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 92cdc4e9a16..f6052b50572 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -78,3 +78,95 @@ "vwmulsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmul") (set_attr "mode" "<V_DOUBLE_TRUNC>")]) + +;; ----------------------------------------------------------------------------- +;; ---- Integer Compare Instructions Simplification +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMCLR.m Includes: +;; - 1. VMSNE +;; - 2. VMSLT +;; - 3. VMSLTU +;; - 4. VMSGT +;; - 5. VMSGTU +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMSET.m Includes: +;; - 1. VMSEQ +;; - 2. VMSLE +;; - 3. VMSLEU +;; - 4. VMSGE +;; - 5. VMSGEU +;; ----------------------------------------------------------------------------- + +(define_split + [(set (match_operand:VB 0 "register_operand") + (if_then_else:VB + (unspec:VB + [(match_operand:VB 1 "vector_all_trues_mask_operand") + (match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VB 3 "vector_move_operand") + (match_operand:VB 2 "vector_undef_operand")))] + "TARGET_VECTOR" + [(const_int 0)] + { + emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode), + RVV_VUNDEF (<MODE>mode), operands[3], + operands[4], operands[5])); + DONE; + } +) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted second input) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmandnot.mm +;; - vmornot.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*<optab>not<mode>" + [(set (match_operand:VB 0 "register_operand" "=vr") + (bitmanip_bitwise:VB + (not:VB (match_operand:VB 2 "register_operand" " vr")) + (match_operand:VB 1 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (<CODE>, <MODE>mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "<MODE>")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted result) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmnand.mm +;; - vmnor.mm +;; - vmxnor.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*n<optab><mode>" + [(set (match_operand:VB 0 "register_operand" "=vr") + (not:VB + (any_bitwise:VB + (match_operand:VB 1 "register_operand" " vr") + (match_operand:VB 2 "register_operand" " vr"))))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (<CODE>, <MODE>mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "<MODE>")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 5c3aad7ee44..4fe0e3253dc 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -228,58 +228,6 @@ [(set_attr "type" "vmalu") (set_attr "mode" "<MODE>")]) -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted second input) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmandnot.mm -;; - vmornot.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*<optab>not<mode>" - [(set (match_operand:VB 0 "register_operand" "=vr") - (bitmanip_bitwise:VB - (not:VB (match_operand:VB 2 "register_operand" " vr")) - (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_not (<CODE>, <MODE>mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "<MODE>")]) - -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted result) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmnand.mm -;; - vmnor.mm -;; - vmxnor.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*n<optab><mode>" - [(set (match_operand:VB 0 "register_operand" "=vr") - (not:VB - (any_bitwise:VB - (match_operand:VB 1 "register_operand" " vr") - (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_n (<CODE>, <MODE>mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "<MODE>")]) - ;; ========================================================================= ;; == Comparisons and selects ;; ========================================================================= diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 79f1644732a..055ad35fde5 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8417,44 +8417,5 @@ [(set_attr "type" "vssegt<order>x") (set_attr "mode" "<V64T:MODE>")]) -;; ----------------------------------------------------------------------------- -;; ---- Integer Compare Instructions Simplification -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMCLR.m Includes: -;; - 1. VMSNE -;; - 2. VMSLT -;; - 3. VMSLTU -;; - 4. VMSGT -;; - 5. VMSGTU -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMSET.m Includes: -;; - 1. VMSEQ -;; - 2. VMSLE -;; - 3. VMSLEU -;; - 4. VMSGE -;; - 5. VMSGEU -;; ----------------------------------------------------------------------------- -(define_split - [(set (match_operand:VB 0 "register_operand") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand") - (match_operand 4 "vector_length_operand") - (match_operand 5 "const_int_operand") - (match_operand 6 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VB 3 "vector_move_operand") - (match_operand:VB 2 "vector_undef_operand")))] - "TARGET_VECTOR" - [(const_int 0)] - { - emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode), - RVV_VUNDEF (<MODE>mode), operands[3], - operands[4], operands[5])); - DONE; - } -) - (include "autovec.md") (include "autovec-opt.md")
next reply other threads:[~2023-06-05 16:18 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-05 16:18 Jeff Law [this message] 2023-07-14 2:42 Jeff Law
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