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From: Alex Coplan <acoplan@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-1615] aarch64: Fix whitespace in ls64 builtin implementation [PR110100] Date: Wed, 7 Jun 2023 16:45:49 +0000 (GMT) [thread overview] Message-ID: <20230607164549.3E38E3858C54@sourceware.org> (raw) https://gcc.gnu.org/g:713613541254039a34e1dd8fd4a613a299af1fd6 commit r14-1615-g713613541254039a34e1dd8fd4a613a299af1fd6 Author: Alex Coplan <alex.coplan@arm.com> Date: Tue Jun 6 11:04:45 2023 +0100 aarch64: Fix whitespace in ls64 builtin implementation [PR110100] The ls64 builtin code was using incorrect GNU style with eight spaces where there should be a tab. Fixed thusly. gcc/ChangeLog: PR target/110100 * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types): Replace eight consecutive spaces with tabs. (aarch64_init_ls64_builtins): Likewise. (aarch64_expand_builtin_ls64): Likewise. * config/aarch64/aarch64.md (ld64b): Likewise. (st64b): Likewise. (st64bv): Likewise (st64bv0): Likewise. Diff: --- gcc/config/aarch64/aarch64-builtins.cc | 64 +++++++++++++++++----------------- gcc/config/aarch64/aarch64.md | 22 ++++++------ 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 50c20c8fa86..d48109139e3 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1862,11 +1862,11 @@ aarch64_init_ls64_builtins_types (void) gcc_assert (TYPE_ALIGN (array_type) == 64); tree field = build_decl (input_location, FIELD_DECL, - get_identifier ("val"), array_type); + get_identifier ("val"), array_type); ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location, - tuple_type_name, - make_array_slice (&field, 1)); + tuple_type_name, + make_array_slice (&field, 1)); gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode); gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t)); @@ -1881,16 +1881,16 @@ aarch64_init_ls64_builtins (void) ls64_builtins_data data[4] = { {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, build_function_type_list (ls64_arm_data_t, - const_ptr_type_node, NULL_TREE)}, + const_ptr_type_node, NULL_TREE)}, {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, build_function_type_list (void_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, build_function_type_list (uint64_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, build_function_type_list (uint64_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, }; for (size_t i = 0; i < ARRAY_SIZE (data); ++i) @@ -2509,40 +2509,40 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) { case AARCH64_LS64_BUILTIN_LD64B: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - create_output_operand (&ops[0], target, V8DImode); - create_input_operand (&ops[1], op0, DImode); - expand_insn (CODE_FOR_ld64b, 2, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + create_output_operand (&ops[0], target, V8DImode); + create_input_operand (&ops[1], op0, DImode); + expand_insn (CODE_FOR_ld64b, 2, ops); + return ops[0].value; } case AARCH64_LS64_BUILTIN_ST64B: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], op0, DImode); - create_input_operand (&ops[1], op1, V8DImode); - expand_insn (CODE_FOR_st64b, 2, ops); - return const0_rtx; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], op0, DImode); + create_input_operand (&ops[1], op1, V8DImode); + expand_insn (CODE_FOR_st64b, 2, ops); + return const0_rtx; } case AARCH64_LS64_BUILTIN_ST64BV: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], target, DImode); - create_input_operand (&ops[1], op0, DImode); - create_input_operand (&ops[2], op1, V8DImode); - expand_insn (CODE_FOR_st64bv, 3, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv, 3, ops); + return ops[0].value; } case AARCH64_LS64_BUILTIN_ST64BV0: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], target, DImode); - create_input_operand (&ops[1], op0, DImode); - create_input_operand (&ops[2], op1, V8DImode); - expand_insn (CODE_FOR_st64bv0, 3, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv0, 3, ops); + return ops[0].value; } } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c2ba726f8a0..11d0d9c8eb6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7918,9 +7918,9 @@ ;; Load/Store 64-bit (LS64) instructions. (define_insn "ld64b" [(set (match_operand:V8DI 0 "register_operand" "=r") - (unspec_volatile:V8DI - [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] - UNSPEC_LD64B) + (unspec_volatile:V8DI + [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] + UNSPEC_LD64B) )] "TARGET_LS64" "ld64b\\t%0, [%1]" @@ -7929,8 +7929,8 @@ (define_insn "st64b" [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) - (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] - UNSPEC_ST64B) + (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] + UNSPEC_ST64B) )] "TARGET_LS64" "st64b\\t%1, [%0]" @@ -7939,10 +7939,10 @@ (define_insn "st64bv" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) - (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] - UNSPEC_ST64BV) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV) )] "TARGET_LS64" "st64bv\\t%0, %2, [%1]" @@ -7951,10 +7951,10 @@ (define_insn "st64bv0" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) - (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] - UNSPEC_ST64BV0) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV0) )] "TARGET_LS64" "st64bv0\\t%0, %2, [%1]"
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