From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2059) id 322CC3857724; Wed, 7 Jun 2023 17:38:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 322CC3857724 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686159529; bh=hf1Z5AJT+GZayd5N2f1siiOsPUh5HKIXYmheN3Vh5LQ=; h=From:To:Subject:Date:From; b=WOUrw1N8Chlns3sMYRo0gPIfdf3ZFJRGBize6NsZ1SSzlh9aJL+uJ7hpqXKcZdjNW YATajJxJG8DbWJCCAm3nxp14X252T6ZhpLq53MHtSfPSGKwQBLtZUDHxvN8g4AClOF pnlpC0MWrat9u+o7tgsdEGIl8wLz0UYoOvm92ffg= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Dimitar Dimitrov To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-1621] riscv: Fix scope for memory model calculation X-Act-Checkin: gcc X-Git-Author: Dimitar Dimitrov X-Git-Refname: refs/heads/master X-Git-Oldrev: ae6c2d1edf289a8a04557e8fbfd4a61841c53345 X-Git-Newrev: 7f26e76c9848aeea9ec10ea701a6168464a4a9c2 Message-Id: <20230607173849.322CC3857724@sourceware.org> Date: Wed, 7 Jun 2023 17:38:49 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7f26e76c9848aeea9ec10ea701a6168464a4a9c2 commit r14-1621-g7f26e76c9848aeea9ec10ea701a6168464a4a9c2 Author: Dimitar Dimitrov Date: Mon Jun 5 21:39:16 2023 +0300 riscv: Fix scope for memory model calculation During libgcc configure stage for riscv32-none-elf, when "--enable-checking=yes,rtl" has been activated, the following error is observed: during RTL pass: final conftest.c: In function 'main': conftest.c:16:1: internal compiler error: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462 16 | } | ^ 0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) /mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916 0x8ea823 riscv_print_operand /mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462 0xde84b5 output_operand(rtx_def*, int) /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632 0xde8ef8 output_asm_insn(char const*, rtx_def**) /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544 0xded33b output_asm_insn(char const*, rtx_def**) /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421 0xded33b final_scan_insn_1 /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841 0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887 0xded8b7 final_1 /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979 0xdee518 rest_of_handle_final /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240 0xdee518 execute /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318 Fix by moving the calculation of memmodel to the cases where it is used. Regression tested for riscv32-none-elf. No changes in gcc.sum and g++.sum. PR target/109725 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Calculate memmodel only when it is valid. Signed-off-by: Dimitar Dimitrov Diff: --- gcc/config/riscv/riscv.cc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4ff3758434c..60ebd9903e5 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4459,7 +4459,6 @@ riscv_print_operand (FILE *file, rtx op, int letter) } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); - const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -4596,7 +4595,8 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (GET_RTX_NAME (code), file); break; - case 'A': + case 'A': { + const enum memmodel model = memmodel_base (INTVAL (op)); if (riscv_memmodel_needs_amo_acquire (model) && riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); @@ -4605,18 +4605,23 @@ riscv_print_operand (FILE *file, rtx op, int letter) else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; + } - case 'I': + case 'I': { + const enum memmodel model = memmodel_base (INTVAL (op)); if (model == MEMMODEL_SEQ_CST) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; + } - case 'J': + case 'J': { + const enum memmodel model = memmodel_base (INTVAL (op)); if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; + } case 'i': if (code != REG)