From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id DE9993858C54; Wed, 7 Jun 2023 18:57:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DE9993858C54 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686164278; bh=YqZow06yM5keph7trFJ+QwoTmbt6wDODU5bb4HBOrFE=; h=From:To:Subject:Date:From; b=BNS/CTuI/YSmyln2m8LSWwZFDKhPxyJB3TQtGBsuVmSZSz1eOb6xLhEQTESibTwhi 1C6F06PFXnZ/2c5NxT+iCUQwyoaIx6I1UJjDVphFodKPWNtRXgz5gmFSeJuEXshvHv bOoaamVsknJ2ZOAfnf40+8evcPGgDMSC/+DU0H0w= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work122)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work122 X-Git-Oldrev: dc15fa44d7cf7eaab9dbefe81de828ae32d20589 X-Git-Newrev: 415f216b7a5559f3cb6eed910820e6be9da5cd15 Message-Id: <20230607185758.DE9993858C54@sourceware.org> Date: Wed, 7 Jun 2023 18:57:58 +0000 (GMT) List-Id: https://gcc.gnu.org/g:415f216b7a5559f3cb6eed910820e6be9da5cd15 commit 415f216b7a5559f3cb6eed910820e6be9da5cd15 Author: Michael Meissner Date: Wed Jun 7 14:57:56 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 108f9865e9e..98e7004b034 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,56 @@ +==================== Branch work122, patch #1 ==================== + +Fix power10 fusion and -fstack-protector, PR target/105325 + +This patch fixes an issue where if you use the -fstack-protector and +-mcpu=power10 options and you have a large stack frame, the GCC compiler will +generate a LWA instruction with a large offset. + +There are several problems: + + 1) The prefixed attribute was not checking insns with the type + fused_load_cmpi for being load insns. + + 2) The recognition of LWA for being prefixed looks at the "sign_extend" + attribute and whether the register mode was different than the memory + load (i.e. does it have a sign_extend wrapper around the load). + + 3) The constraints in fusion.md (generated by genfusion.pl) use "m" for LWA + and LD, when they should use "YZ". + + 4) There is a lwa_operand that should be used instead of + ds_form_mem_operand for the LWA instruction. + +The main fix is to modify genfusion.pl that it sets the appropriate predicates +and constraints. + +I also added support in genfusion.md so that if we are doing a LWA operation and +just setting the CC bits (throwing away the result of the load after the +comparison), it generates a LWZ instruction and does a CMPWI instead of CMPDI. +This way those loads can use normal D-FORM restrictions instead of DS-form. + +I set the "sign_extend" attribute on the cases that generate LWA. + +I modified the "prefixed" attribute so that it also checks fused_load_cmpi. + +2023-06-06 Michael Meissner + +gcc/ + + * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix constraints and + predicates for LD and LWA. Optimize LWA/CMPDI to generate LWZ/CMPWI if + we don't need the result of the load after the comparison. Change the + name of the insn pattern to reflect whether a DImode or SImode register + is loaded. Set sign_extend attribute for LWA instruction. + * config/rs6000/fusion.md: Regenerate. + * config/rs6000/rs6000.md (prefixed attribute): Treat fused_load_cmpi + insns as being load insns. + +gcc/testsuite/ + + * g++.target/powerpc/pr105325.C: New test. + + ==================== Branch work122, baseline ==================== 2023-06-06 Michael Meissner