From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 401DD385840D; Mon, 19 Jun 2023 11:41:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 401DD385840D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687174896; bh=gfs1yZIT6eiyKaOgK1IHeifrl3dA4CNaDdhRc1VQl4k=; h=From:To:Subject:Date:From; b=SXdN+lAl1YMeAWdIfjuhlbKnkGFoiCr+D56ksd+D2ko2P3RzdRkAW/+z+ATY4VWPc dgg/bp4aW4u65I7YXvWWcztEcEhoVz07W26+y39UwLSr8bzxdkpEj23bD9XyKJJZ1f IBqG/5TDRLjfeVaM/vxnPHnbd7XelYjYgTONKQ5w= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Ensure vector args and return use function stack to pass [PR110119] X-Act-Checkin: gcc X-Git-Author: Lehua Ding X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 424975c5d136cd5002d107945500c86c4dc50d85 X-Git-Newrev: d468ad1db10828c6ea217f00f9b3399f37c8c650 Message-Id: <20230619114136.401DD385840D@sourceware.org> Date: Mon, 19 Jun 2023 11:41:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d468ad1db10828c6ea217f00f9b3399f37c8c650 commit d468ad1db10828c6ea217f00f9b3399f37c8c650 Author: Lehua Ding Date: Wed Jun 14 19:56:11 2023 +0800 RISC-V: Ensure vector args and return use function stack to pass [PR110119] The V2 patch address comments from Juzhe, thanks. Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed through two scalar registers, but when GCC calls FUNCTION_VALUE (call function riscv_get_arg_info inside) it returns NULL_RTX. These two functions are not unified. The current treatment is to pass all vector arguments and returns through the function stack, and a new calling convention for vector registers will be added in the future. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/ https://github.com/palmer-dabbelt/riscv-elf-psabi-doc/commit/126fa719972ff998a8a239c47d506c7809aea363 Best, Lehua gcc/ChangeLog: PR target/110119 * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode (riscv_pass_by_reference): Return true for vector mode gcc/testsuite/ChangeLog: PR target/110119 * gcc.target/riscv/rvv/base/pr110119-1.c: New test. * gcc.target/riscv/rvv/base/pr110119-2.c: New test. Diff: --- gcc/config/riscv/riscv.cc | 17 +++++++++----- .../gcc.target/riscv/rvv/base/pr110119-1.c | 26 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr110119-2.c | 26 ++++++++++++++++++++++ 3 files changed, 64 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dd5361c2bd2..e5ae4e81b7a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3915,13 +3915,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, riscv_pass_in_vector_p (type); } - /* TODO: Currently, it will cause an ICE for --param - riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here - let GCC generate loads/stores. Ideally, we should either warn the user not - to use an RVV vector type as function argument or support the calling - convention directly. */ + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ if (riscv_v_ext_mode_p (mode)) return NULL_RTX; + if (named) { riscv_aggregate_field fields[2]; @@ -4106,6 +4106,13 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) return false; } + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (arg.mode)) + return true; + /* Pass by reference if the data do not fit in two integer registers. */ return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c new file mode 100644 index 00000000000..f16502bcfee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + return v; +} + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi_2 (vnx2qi a, int8_t *out) +{ + return a; +} + +__attribute__ ((noipa)) vint32m1_t +f_vint32m1 (int8_t *a, int8_t *out) +{ + vint32m1_t v = *(vint32m1_t *) a; + return v; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c new file mode 100644 index 00000000000..b233ff1e904 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include +#include "riscv_vector.h" + +__attribute__ ((noipa)) vint32m1x3_t +foo1 (int32_t *in, int vl) +{ + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +} + +__attribute__ ((noipa)) void +foo2 (vint32m1x3_t a, int32_t *out, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); +} + +__attribute__ ((noipa)) vint32m1x3_t +foo3 (vint32m1x3_t a, int32_t *out, int32_t *in, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +}