From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 8059B3857B9B; Sat, 24 Jun 2023 14:43:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8059B3857B9B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687617820; bh=lRoW7FsYvqi+LoMAOqvndu9WDQ1O5SGrMKg41OVXYQc=; h=From:To:Subject:Date:From; b=Zryh1i0PanBSMU++HHafyghkAoWBprCDTyUNChPWSGX02xWqPC02xPnCWwMuyXvz1 tBj6zlNmSMsYxga0SAjNChyf+eUcdPXg6kb5I5bkGUXx7HwW2RTGPGmB/vaaVpc06Y RQtjyl+BLaw+Qp8uGaW8taLIpENkNlS5nEpI7bX0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-2063] RISC-V: Refactor the integer ternary autovec pattern X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 0a3b1a095d451427571299fc78f29dec94c6931c X-Git-Newrev: 95a2e5328e5aa15724ab8da4aa622a0bfc40c9e5 Message-Id: <20230624144340.8059B3857B9B@sourceware.org> Date: Sat, 24 Jun 2023 14:43:40 +0000 (GMT) List-Id: https://gcc.gnu.org/g:95a2e5328e5aa15724ab8da4aa622a0bfc40c9e5 commit r14-2063-g95a2e5328e5aa15724ab8da4aa622a0bfc40c9e5 Author: Juzhe-Zhong Date: Thu Jun 22 06:38:42 2023 +0800 RISC-V: Refactor the integer ternary autovec pattern Long time ago, I encounter ICE when trying to set clobber register as Pmode and I forgot the reason. So, I clobber SI scratch and PUT_MODE to make it Pmode after reload which makes patterns look unreasonable. According to Jeff's comments, I tried it again, it works now when we try to set clobber register as Pmode and the patterns look more reasonable now. The tests are all passed, Ok for trunk. gcc/ChangeLog: * config/riscv/autovec.md (*fma): set clobber to Pmode in expand stage. (*fma): Ditto. (*fnma): Ditto. (*fnma): Ditto. Diff: --- gcc/config/riscv/autovec.md | 54 +++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index cf154b3737a..731ffe8ff89 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -596,40 +596,41 @@ ;; result after reload_completed. (define_expand "fma4" [(parallel - [(set (match_operand:VI 0 "register_operand" "=vr") + [(set (match_operand:VI 0 "register_operand") (plus:VI (mult:VI - (match_operand:VI 1 "register_operand" " vr") - (match_operand:VI 2 "register_operand" " vr")) - (match_operand:VI 3 "register_operand" " vr"))) - (clobber (match_scratch:SI 4))])] + (match_operand:VI 1 "register_operand") + (match_operand:VI 2 "register_operand")) + (match_operand:VI 3 "register_operand"))) + (clobber (match_dup 4))])] "TARGET_VECTOR" - {}) + { + operands[4] = gen_reg_rtx (Pmode); + }) -(define_insn_and_split "*fma" +(define_insn_and_split "*fma" [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr") (plus:VI (mult:VI (match_operand:VI 1 "register_operand" " %0, vr, vr") (match_operand:VI 2 "register_operand" " vr, vr, vr")) (match_operand:VI 3 "register_operand" " vr, 0, vr"))) - (clobber (match_scratch:SI 4 "=r,r,r"))] + (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { - PUT_MODE (operands[4], Pmode); - riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); + riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); if (which_alternative == 2) emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; - riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), - riscv_vector::RVV_TERNOP, ops, operands[4]); + riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), + riscv_vector::RVV_TERNOP, ops, operands[4]); DONE; } [(set_attr "type" "vimuladd") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] VNMSAC and VNMSUB @@ -641,40 +642,41 @@ (define_expand "fnma4" [(parallel - [(set (match_operand:VI 0 "register_operand" "=vr") + [(set (match_operand:VI 0 "register_operand") (minus:VI - (match_operand:VI 3 "register_operand" " vr") + (match_operand:VI 3 "register_operand") (mult:VI - (match_operand:VI 1 "register_operand" " vr") - (match_operand:VI 2 "register_operand" " vr")))) - (clobber (match_scratch:SI 4))])] + (match_operand:VI 1 "register_operand") + (match_operand:VI 2 "register_operand")))) + (clobber (match_dup 4))])] "TARGET_VECTOR" - {}) + { + operands[4] = gen_reg_rtx (Pmode); + }) -(define_insn_and_split "*fnma" +(define_insn_and_split "*fnma" [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr") (minus:VI (match_operand:VI 3 "register_operand" " vr, 0, vr") (mult:VI (match_operand:VI 1 "register_operand" " %0, vr, vr") (match_operand:VI 2 "register_operand" " vr, vr, vr")))) - (clobber (match_scratch:SI 4 "=r,r,r"))] + (clobber (match_operand:P 4 "register_operand" "=r,r,r"))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { - PUT_MODE (operands[4], Pmode); - riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); + riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); if (which_alternative == 2) emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; - riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), - riscv_vector::RVV_TERNOP, ops, operands[4]); + riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), + riscv_vector::RVV_TERNOP, ops, operands[4]); DONE; } [(set_attr "type" "vimuladd") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------- ;; ---- [FP] VFMACC and VFMADD