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From: GCC Administrator <gccadmin@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-2081] Daily bump. Date: Mon, 26 Jun 2023 00:17:51 +0000 (GMT) [thread overview] Message-ID: <20230626001751.AD88C3858D20@sourceware.org> (raw) https://gcc.gnu.org/g:f445b42e1881fe875c61ad8f7aa080121dd89ab3 commit r14-2081-gf445b42e1881fe875c61ad8f7aa080121dd89ab3 Author: GCC Administrator <gccadmin@gcc.gnu.org> Date: Mon Jun 26 00:17:28 2023 +0000 Daily bump. Diff: --- ChangeLog | 12 +++++ gcc/ChangeLog | 128 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/d/ChangeLog | 5 ++ gcc/testsuite/ChangeLog | 52 ++++++++++++++++++++ libphobos/ChangeLog | 5 ++ 6 files changed, 203 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index 1965414b471..96a4056e42c 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2023-06-25 Lehua Ding <lehua.ding@rivai.ai> + + * MAINTAINERS: Add Lehua Ding to write after approval + +2023-06-25 Iain Sandoe <iain@sandoe.co.uk> + + * Makefile.def: Pass the enable-host-pie value to GCC configure. + * Makefile.in: Regenerate. + * configure: Regenerate. + * configure.ac: Adjust the logic for shared and PIE host flags to + ensure that PIE is passed for hosts that require it. + 2023-06-16 YunQiang Su <yunqiang.su@cipunited.com> * MAINTAINERS (Write After Approval): move Matthew Fortune diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bed2c100da..a7d51b5038a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,131 @@ +2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (vector_insn_info::parse_insn): Ehance + AVL propagation. + * config/riscv/riscv-vsetvl.h: New function. + +2023-06-25 Li Xu <xuli1@eswincomputing.com> + + * config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to + emit_move_insn + +2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec.md (len_load_<mode>): Remove. + (len_maskload<mode><vm>): Remove. + (len_store_<mode>): New pattern. + (len_maskstore<mode><vm>): New pattern. + * config/riscv/predicates.md (autovec_length_operand): New predicate. + * config/riscv/riscv-protos.h (enum insn_type): New enum. + (expand_load_store): New function. + * config/riscv/riscv-v.cc (emit_vlmax_masked_insn): Ditto. + (emit_nonvlmax_masked_insn): Ditto. + (expand_load_store): Ditto. + * config/riscv/riscv-vector-builtins.cc + (function_expander::use_contiguous_store_insn): Add avl_type operand + into pred_store. + * config/riscv/vector.md: Ditto. + +2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * internal-fn.cc (expand_partial_store_optab_fn): Fix bug of BIAS + argument index. + +2023-06-25 Pan Li <pan2.li@intel.com> + + * config/riscv/vector.md: Revert. + +2023-06-25 Pan Li <pan2.li@intel.com> + + * config/riscv/genrvv-type-indexer.cc (valid_type): Revert changes. + * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): Ditto. + (ADJUST_ALIGNMENT): Ditto. + (RVV_TUPLE_PARTIAL_MODES): Ditto. + (ADJUST_NUNITS): Ditto. + * config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t): Ditto. + (vfloat16mf4x3_t): Ditto. + (vfloat16mf4x4_t): Ditto. + (vfloat16mf4x5_t): Ditto. + (vfloat16mf4x6_t): Ditto. + (vfloat16mf4x7_t): Ditto. + (vfloat16mf4x8_t): Ditto. + (vfloat16mf2x2_t): Ditto. + (vfloat16mf2x3_t): Ditto. + (vfloat16mf2x4_t): Ditto. + (vfloat16mf2x5_t): Ditto. + (vfloat16mf2x6_t): Ditto. + (vfloat16mf2x7_t): Ditto. + (vfloat16mf2x8_t): Ditto. + (vfloat16m1x2_t): Ditto. + (vfloat16m1x3_t): Ditto. + (vfloat16m1x4_t): Ditto. + (vfloat16m1x5_t): Ditto. + (vfloat16m1x6_t): Ditto. + (vfloat16m1x7_t): Ditto. + (vfloat16m1x8_t): Ditto. + (vfloat16m2x2_t): Ditto. + (vfloat16m2x3_t): Diito. + (vfloat16m2x4_t): Diito. + (vfloat16m4x2_t): Diito. + * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Ditto. + (vfloat16mf4x3_t): Ditto. + (vfloat16mf4x4_t): Ditto. + (vfloat16mf4x5_t): Ditto. + (vfloat16mf4x6_t): Ditto. + (vfloat16mf4x7_t): Ditto. + (vfloat16mf4x8_t): Ditto. + (vfloat16mf2x2_t): Ditto. + (vfloat16mf2x3_t): Ditto. + (vfloat16mf2x4_t): Ditto. + (vfloat16mf2x5_t): Ditto. + (vfloat16mf2x6_t): Ditto. + (vfloat16mf2x7_t): Ditto. + (vfloat16mf2x8_t): Ditto. + (vfloat16m1x2_t): Ditto. + (vfloat16m1x3_t): Ditto. + (vfloat16m1x4_t): Ditto. + (vfloat16m1x5_t): Ditto. + (vfloat16m1x6_t): Ditto. + (vfloat16m1x7_t): Ditto. + (vfloat16m1x8_t): Ditto. + (vfloat16m2x2_t): Ditto. + (vfloat16m2x3_t): Ditto. + (vfloat16m2x4_t): Ditto. + (vfloat16m4x2_t): Ditto. + * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto. + * config/riscv/riscv.md: Ditto. + * config/riscv/vector-iterators.md: Ditto. + +2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * gimple-fold.cc (arith_overflowed_p): Apply LEN_MASK_{LOAD,STORE}. + (gimple_fold_partial_load_store_mem_ref): Ditto. + (gimple_fold_partial_store): Ditto. + (gimple_fold_call): Ditto. + +2023-06-25 liuhongt <hongtao.liu@intel.com> + + PR target/110309 + * config/i386/sse.md (maskload<mode><avx512fmaskmodelower>): + Refine pattern with UNSPEC_MASKLOAD. + (maskload<mode><avx512fmaskmodelower>): Ditto. + (*<avx512>_load<mode>_mask): Extend mode iterator to + VI12HFBF_AVX512VL. + (*<avx512>_load<mode>): Ditto. + +2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * tree-ssa-alias.cc (call_may_clobber_ref_p_1): Add LEN_MASK_STORE. + +2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Apply + LEN_MASK_{LOAD,STORE} + +2023-06-25 yulong <shiyulong@iscas.ac.cn> + + * config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio. + 2023-06-24 Roger Sayle <roger@nextmovesoftware.com> * config/i386/i386.md (*<code>qi_ext<mode>_3): New define_insn. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 2ee91bf4891..2cf61a4ffbf 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230625 +20230626 diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 87482833dd0..add868843e9 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,8 @@ +2023-06-25 Iain Buclaw <ibuclaw@gdcproject.org> + + * dmd/MERGE: Merge upstream dmd a45f4e9f43. + * dmd/VERSION: Bump version to v2.103.1. + 2023-06-15 Marek Polacek <polacek@redhat.com> * Make-lang.in: Remove NO_PIE_CFLAGS. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f39e15f61f..470cff2ff1c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,55 @@ +2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Add dump checks. + * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: New test. + +2023-06-25 Li Xu <xuli1@eswincomputing.com> + + * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test. + +2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: New test. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.h: New test. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: New test. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h: New test. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: New test. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: New test. + +2023-06-25 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/base/abi-10.c: Revert. + * gcc.target/riscv/rvv/base/abi-11.c: Ditto. + * gcc.target/riscv/rvv/base/abi-12.c: Ditto. + * gcc.target/riscv/rvv/base/abi-15.c: Ditto. + * gcc.target/riscv/rvv/base/abi-8.c: Ditto. + * gcc.target/riscv/rvv/base/abi-9.c: Ditto. + * gcc.target/riscv/rvv/base/abi-17.c: Ditto. + * gcc.target/riscv/rvv/base/abi-18.c: Ditto. + +2023-06-25 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/base/tuple-28.c: Removed. + * gcc.target/riscv/rvv/base/tuple-29.c: Removed. + * gcc.target/riscv/rvv/base/tuple-30.c: Removed. + * gcc.target/riscv/rvv/base/tuple-31.c: Removed. + * gcc.target/riscv/rvv/base/tuple-32.c: Removed. + +2023-06-25 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/pr110309.c: New test. + +2023-06-25 yulong <shiyulong@iscas.ac.cn> + + * gcc.target/riscv/rvv/base/abi-10.c: Add float16 tuple type case. + * gcc.target/riscv/rvv/base/abi-11.c: Ditto. + * gcc.target/riscv/rvv/base/abi-12.c: Ditto. + * gcc.target/riscv/rvv/base/abi-15.c: Ditto. + * gcc.target/riscv/rvv/base/abi-8.c: Ditto. + * gcc.target/riscv/rvv/base/abi-9.c: Ditto. + * gcc.target/riscv/rvv/base/abi-17.c: New test. + * gcc.target/riscv/rvv/base/abi-18.c: New test. + 2023-06-24 Juzhe-Zhong <juzhe.zhong@rivai.ai> * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Adjust tests. diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog index 70d4f557d1c..d3ceebf653e 100644 --- a/libphobos/ChangeLog +++ b/libphobos/ChangeLog @@ -1,3 +1,8 @@ +2023-06-25 Iain Buclaw <ibuclaw@gdcproject.org> + + * libdruntime/MERGE: Merge upstream druntime a45f4e9f43. + * src/MERGE: Merge upstream phobos 106038f2e. + 2023-03-17 Iain Buclaw <ibuclaw@gdcproject.org> * libdruntime/MERGE: Merge upstream druntime 5f7552bb28.
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