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From: Kyrylo Tkachov <ktkachov@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-2106] aarch64: Clean up some rounding immediate predicates Date: Mon, 26 Jun 2023 16:54:22 +0000 (GMT) [thread overview] Message-ID: <20230626165422.5BB2D3858D1E@sourceware.org> (raw) https://gcc.gnu.org/g:198bab37a93526af1a4419cb7244f2bb5a16415b commit r14-2106-g198bab37a93526af1a4419cb7244f2bb5a16415b Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com> Date: Mon Jun 26 17:52:49 2023 +0100 aarch64: Clean up some rounding immediate predicates aarch64_simd_rsra_rnd_imm_vec is now used for more than just RSRA and accepts more than just vectors so rename it to make it more truthful. The aarch64_simd_rshrn_imm_vec is now unused and can be deleted. No behavioural change intended. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-protos.h (aarch64_const_vec_rsra_rnd_imm_p): Rename to... (aarch64_rnd_imm_p): ... This. * config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec): Rename to... (aarch64_int_rnd_operand): ... This. (aarch64_simd_rshrn_imm_vec): Delete. * config/aarch64/aarch64-simd.md (aarch64_<sra_op>rsra_n<mode>_insn): Adjust for the above. (aarch64_<sra_op>rshr_n<mode><vczle><vczbe>_insn): Likewise. (*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise. (*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>): Likewise. (aarch64_sqrshrun_n<mode>_insn): Likewise. (aarch64_<shrn_op>rshrn2_n<mode>_insn_le): Likewise. (aarch64_<shrn_op>rshrn2_n<mode>_insn_be): Likewise. (aarch64_sqrshrun2_n<mode>_insn_le): Likewise. (aarch64_sqrshrun2_n<mode>_insn_be): Likewise. * config/aarch64/aarch64.cc (aarch64_const_vec_rsra_rnd_imm_p): Rename to... (aarch64_rnd_imm_p): ... This. Diff: --- gcc/config/aarch64/aarch64-protos.h | 2 +- gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++---------- gcc/config/aarch64/aarch64.cc | 10 +++++----- gcc/config/aarch64/predicates.md | 12 ++++-------- 4 files changed, 20 insertions(+), 24 deletions(-) diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index a20a20ce15f..70303d6fd95 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -759,7 +759,7 @@ bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT); bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); bool aarch64_const_vec_rnd_cst_p (rtx, rtx); -bool aarch64_const_vec_rsra_rnd_imm_p (rtx); +bool aarch64_rnd_imm_p (rtx); bool aarch64_constant_address_p (rtx); bool aarch64_emit_approx_div (rtx, rtx, rtx); bool aarch64_emit_approx_sqrt (rtx, rtx, bool); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 90118c6348e..0ea112346b0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1323,7 +1323,7 @@ (plus:<V2XWIDE> (<SHIFTEXTEND>:<V2XWIDE> (match_operand:VSDQ_I_DI 2 "register_operand" "w")) - (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand")) (match_operand:VSDQ_I_DI 3 "aarch64_simd_shift_imm_<vec_or_offset>_<Vel>"))) (match_operand:VSDQ_I_DI 1 "register_operand" "0")))] "TARGET_SIMD @@ -6437,7 +6437,7 @@ (plus:<V2XWIDE> (<SHIFTEXTEND>:<V2XWIDE> (match_operand:VSDQ_I_DI 1 "register_operand" "w")) - (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand")) (match_operand:VSDQ_I_DI 2 "aarch64_simd_shift_imm_<vec_or_offset>_<Vel>"))))] "TARGET_SIMD && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])" @@ -6557,7 +6557,7 @@ (plus:<V2XWIDE> (<TRUNCEXTEND>:<V2XWIDE> (match_operand:VQN 1 "register_operand" "w")) - (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand")) (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_<vn_mode>"))))] "TARGET_SIMD && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])" @@ -6572,7 +6572,7 @@ (plus:<DWI> (<TRUNCEXTEND>:<DWI> (match_operand:SD_HSDI 1 "register_operand" "w")) - (match_operand:<DWI> 3 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<DWI> 3 "aarch64_int_rnd_operand")) (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))] "TARGET_SIMD && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])" @@ -6702,7 +6702,7 @@ (plus:<V2XWIDE> (sign_extend:<V2XWIDE> (match_operand:VQN 1 "register_operand" "w")) - (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand")) (match_operand:VQN 2 "aarch64_simd_shift_imm_vec_<vn_mode>")) (match_operand:<V2XWIDE> 4 "aarch64_simd_imm_zero")) (match_operand:<V2XWIDE> 5 "aarch64_simd_umax_quarter_mode"))))] @@ -6720,7 +6720,7 @@ (plus:<V2XWIDE> (sign_extend:<V2XWIDE> (match_operand:SD_HSDI 1 "register_operand" "w")) - (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand")) (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>")) (const_int 0)) (const_int <half_mask>)))] @@ -6831,7 +6831,7 @@ (plus:<V2XWIDE> (<TRUNCEXTEND>:<V2XWIDE> (match_operand:VQN 2 "register_operand" "w")) - (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand")) (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>")))))] "TARGET_SIMD && !BYTES_BIG_ENDIAN && aarch64_const_vec_rnd_cst_p (operands[4], operands[3])" @@ -6847,7 +6847,7 @@ (plus:<V2XWIDE> (<TRUNCEXTEND>:<V2XWIDE> (match_operand:VQN 2 "register_operand" "w")) - (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand")) (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>"))) (match_operand:<VNARROWQ> 1 "register_operand" "0")))] "TARGET_SIMD && BYTES_BIG_ENDIAN @@ -6965,7 +6965,7 @@ (plus:<V2XWIDE> (sign_extend:<V2XWIDE> (match_operand:VQN 2 "register_operand" "w")) - (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand")) (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>")) (match_operand:<V2XWIDE> 5 "aarch64_simd_imm_zero")) (match_operand:<V2XWIDE> 6 "aarch64_simd_umax_quarter_mode")))))] @@ -6985,7 +6985,7 @@ (plus:<V2XWIDE> (sign_extend:<V2XWIDE> (match_operand:VQN 2 "register_operand" "w")) - (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand")) (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>")) (match_operand:<V2XWIDE> 5 "aarch64_simd_imm_zero")) (match_operand:<V2XWIDE> 6 "aarch64_simd_umax_quarter_mode"))) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 644ebdebc0e..560e5431636 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -11761,14 +11761,14 @@ aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi) return true; } -/* Return true if X is a TImode constant or a constant vector of integer - immediates that represent the rounding constant used in the RSRA - instructions. - The accepted form of the constant is (1 << (C - 1)) where C is within +/* Return true if X is a scalar or a constant vector of integer + immediates that represent the rounding constant used in the fixed-point + arithmetic instructions. + The accepted form of the constant is (1 << (C - 1)) where C is in the range [1, MODE_WIDTH/2]. */ bool -aarch64_const_vec_rsra_rnd_imm_p (rtx x) +aarch64_rnd_imm_p (rtx x) { wide_int rnd_cst; if (!aarch64_extract_vec_duplicate_wide_int (x, &rnd_cst)) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index b31ba6ee1d5..d5a4a1cd9bf 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -626,15 +626,11 @@ (and (match_code "const_vector") (match_test "aarch64_const_vec_all_same_in_range_p (op, 1, 64)"))) -(define_predicate "aarch64_simd_rsra_rnd_imm_vec" +;; A constant or vector of constants that represents an integer rounding +;; constant added during fixed-point arithmetic calculations +(define_predicate "aarch64_int_rnd_operand" (and (match_code "const_vector,const_int,const_wide_int") - (match_test "aarch64_const_vec_rsra_rnd_imm_p (op)"))) - -(define_predicate "aarch64_simd_rshrn_imm_vec" - (and (match_code "const_vector") - (match_test "aarch64_const_vec_all_same_in_range_p (op, 1, - HOST_WIDE_INT_1U - << (GET_MODE_UNIT_BITSIZE (mode) - 1))"))) + (match_test "aarch64_rnd_imm_p (op)"))) (define_predicate "aarch64_simd_raddsubhn_imm_vec" (and (match_code "const_vector")
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