From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 62F80385840D; Mon, 26 Jun 2023 20:57:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 62F80385840D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687813063; bh=brthpde83VSCvO/Vm4d5+EZFMFTji9psBam0RMVZwZk=; h=From:To:Subject:Date:From; b=uY7Xgb8obqrzca3D49FXI9p290MBpPaX+klVJARP3+6CawufsJvhJLYa+2pcRlBM6 rr1FtmVsaZpo3+ZKRQLFZQOd0ANRvygTpuuF+QEJ0B3u7zHqVUeUma5dO2Xv4dNtIA W6mIkaKDHceE/KQdXAVvbCraKoOd/jP/vDgwIyfg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove redundant vcond patterns X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: cee722a403bede41bde74fe9aabad82c63015cf3 X-Git-Newrev: 5adbb7e84f39bfbcf70baf5370c7cb44b02b8c63 Message-Id: <20230626205743.62F80385840D@sourceware.org> Date: Mon, 26 Jun 2023 20:57:43 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5adbb7e84f39bfbcf70baf5370c7cb44b02b8c63 commit 5adbb7e84f39bfbcf70baf5370c7cb44b02b8c63 Author: Juzhe-Zhong Date: Mon Jun 26 11:38:30 2023 +0800 RISC-V: Remove redundant vcond patterns Previously, Richi has suggested that vcond patterns are only needed when target support comparison + select consuming 1 instruction. Now, I do the experiments on removing those "vcond" patterns, it works perfectly. All testcases PASS. Really appreicate Richi helps us recognize such issue. Now remove all "vcond" patterns as Richi suggested. gcc/ChangeLog: * config/riscv/autovec.md (vcond): Remove redundant vcond patterns. (vcondu): Ditto. * config/riscv/riscv-protos.h (expand_vcond): Ditto. * config/riscv/riscv-v.cc (expand_vcond): Ditto. Diff: --- gcc/config/riscv/autovec.md | 38 -------------------------------------- gcc/config/riscv/riscv-protos.h | 1 - gcc/config/riscv/riscv-v.cc | 22 ---------------------- 3 files changed, 61 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 5de43a8d647..19100b5b2cb 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -311,44 +311,6 @@ } ) -;; ------------------------------------------------------------------------- -;; ---- [INT,FP] Compare and select -;; ------------------------------------------------------------------------- -;; The patterns in this section are synthetic. -;; ------------------------------------------------------------------------- - -(define_expand "vcond" - [(set (match_operand:V 0 "register_operand") - (if_then_else:V - (match_operator 3 "comparison_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")]) - (match_operand:V 1 "register_operand") - (match_operand:V 2 "register_operand")))] - "TARGET_VECTOR && known_eq (GET_MODE_NUNITS (mode), - GET_MODE_NUNITS (mode))" - { - riscv_vector::expand_vcond (operands); - DONE; - } -) - -(define_expand "vcondu" - [(set (match_operand:V 0 "register_operand") - (if_then_else:V - (match_operator 3 "comparison_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")]) - (match_operand:V 1 "register_operand") - (match_operand:V 2 "register_operand")))] - "TARGET_VECTOR && known_eq (GET_MODE_NUNITS (mode), - GET_MODE_NUNITS (mode))" - { - riscv_vector::expand_vcond (operands); - DONE; - } -) - ;; ------------------------------------------------------------------------- ;; ---- [INT] Sign and zero extension ;; ------------------------------------------------------------------------- diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f686edab3d1..7265b1c8401 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -252,7 +252,6 @@ machine_mode preferred_simd_mode (scalar_mode); opt_machine_mode get_mask_mode (machine_mode); void expand_vec_series (rtx, rtx, rtx); void expand_vec_init (rtx, rtx); -void expand_vcond (rtx *); void expand_vec_perm (rtx, rtx, rtx, rtx); void expand_select_vl (rtx *); void expand_load_store (rtx *, bool); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5518394be1e..f6dd0d8e2a4 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2421,28 +2421,6 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, return false; } -/* Expand an RVV vcond pattern with operands OPS. DATA_MODE is the mode - of the data being merged and CMP_MODE is the mode of the values being - compared. */ - -void -expand_vcond (rtx *ops) -{ - machine_mode cmp_mode = GET_MODE (ops[4]); - machine_mode data_mode = GET_MODE (ops[1]); - machine_mode mask_mode = get_mask_mode (cmp_mode).require (); - rtx mask = gen_reg_rtx (mask_mode); - if (FLOAT_MODE_P (cmp_mode)) - { - if (expand_vec_cmp_float (mask, GET_CODE (ops[3]), ops[4], ops[5], true)) - std::swap (ops[1], ops[2]); - } - else - expand_vec_cmp (mask, GET_CODE (ops[3]), ops[4], ops[5]); - emit_insn ( - gen_vcond_mask (data_mode, data_mode, ops[0], ops[1], ops[2], mask)); -} - /* Implement vec_perm. */ void