From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7808) id 10B013858D1E; Wed, 28 Jun 2023 08:39:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 10B013858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687941566; bh=yyYrTK/Ysiqi2FWJWKxqftACzDrajzaBAL/3xNe3Xo4=; h=From:To:Subject:Date:From; b=T2d5PrcxPhekOcxznN2/67/WWTorvFUJfhKTDHdPtxlMlJzOPIeIyx8QcIlXl2xkm 3FrYhLE178lfc+SL3jISOY54tXjCQKX+jZJSdfPBEb7Ma1ZMbuBNUoCsjG65J/RTbs 7g6XyCdm5fDBLiwRWN+pNePIBL4Lf438bPf+6m6k= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: HaoChen Gui To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-2153] rs6000: Splat vector small V2DI constants with vspltisw and vupkhsw X-Act-Checkin: gcc X-Git-Author: Haochen Gui X-Git-Refname: refs/heads/master X-Git-Oldrev: 7198573f44fb579843bff8deda695107858d8cff X-Git-Newrev: f3d87219dd502d5c11608ffb83fbe66c79baf784 Message-Id: <20230628083926.10B013858D1E@sourceware.org> Date: Wed, 28 Jun 2023 08:39:26 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f3d87219dd502d5c11608ffb83fbe66c79baf784 commit r14-2153-gf3d87219dd502d5c11608ffb83fbe66c79baf784 Author: Haochen Gui Date: Wed Jun 28 16:30:44 2023 +0800 rs6000: Splat vector small V2DI constants with vspltisw and vupkhsw This patch adds a new insn for vector splat with small V2DI constants on P8. If the value of constant is in RANGE (-16, 15) but not 0 or -1, it can be loaded with vspltisw and vupkhsw on P8. gcc/ PR target/104124 * config/rs6000/altivec.md (*altivec_vupkhs_direct): Rename to... (altivec_vupkhs_direct): ...this. * config/rs6000/predicates.md (vspltisw_vupkhsw_constant_split): New predicate to test if a constant can be loaded with vspltisw and vupkhsw. (easy_vector_constant): Call vspltisw_vupkhsw_constant_p to Check if a vector constant can be synthesized with a vspltisw and a vupkhsw. * config/rs6000/rs6000-protos.h (vspltisw_vupkhsw_constant_p): Declare. * config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p): New function to return true if OP mode is V2DI and can be synthesized with vupkhsw and vspltisw. * config/rs6000/vsx.md (*vspltisw_v2di_split): New insn to load up constants with vspltisw and vupkhsw. gcc/testsuite/ PR target/104124 * gcc.target/powerpc/pr104124.c: New. Diff: --- gcc/config/rs6000/altivec.md | 2 +- gcc/config/rs6000/predicates.md | 11 +++++++++++ gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.cc | 30 +++++++++++++++++++++++++++++ gcc/config/rs6000/vsx.md | 24 +++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr104124.c | 14 ++++++++++++++ 6 files changed, 81 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index ad1224e0b57..70db5cfcd9f 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2550,7 +2550,7 @@ } [(set_attr "type" "vecperm")]) -(define_insn "*altivec_vupkhs_direct" +(define_insn "altivec_vupkhs_direct" [(set (match_operand:VP 0 "register_operand" "=v") (unspec:VP [(match_operand: 1 "register_operand" "v")] UNSPEC_VUNPACK_HI_SIGN_DIRECT))] diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 6b564837c6e..8479331482e 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -694,6 +694,12 @@ return num_insns > 1; }) +;; Return true if the operand is a constant that can be loaded with a vspltisw +;; instruction and then a vupkhsw instruction. + +(define_predicate "vspltisw_vupkhsw_constant_split" + (and (match_code "const_vector") + (match_test "vspltisw_vupkhsw_constant_p (op, mode)"))) ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB ;; instruction. @@ -742,6 +748,11 @@ && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; + /* V2DI constant within RANGE (-16, 15) can be synthesized with a + vspltisw and a vupkhsw. */ + if (vspltisw_vupkhsw_constant_p (op, mode, &value)) + return true; + return easy_altivec_constant (op, mode); } diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 9a4cc18c6d3..f70118ea40f 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,6 +32,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern int easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); +extern bool vspltisw_vupkhsw_constant_p (rtx, machine_mode, int * = nullptr); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 546c353029b..07c3a3d15ac 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6642,6 +6642,36 @@ xxspltib_constant_p (rtx op, return true; } +/* Return true if OP mode is V2DI and can be synthesized with ISA 2.07 + instructions vupkhsw and vspltisw. + + Return the constant that is being split via CONSTANT_PTR. */ + +bool +vspltisw_vupkhsw_constant_p (rtx op, machine_mode mode, int *constant_ptr) +{ + HOST_WIDE_INT value; + rtx elt; + + if (!TARGET_P8_VECTOR) + return false; + + if (mode != V2DImode) + return false; + + if (!const_vec_duplicate_p (op, &elt)) + return false; + + value = INTVAL (elt); + if (value == 0 || value == 1 + || !EASY_VECTOR_15 (value)) + return false; + + if (constant_ptr) + *constant_ptr = (int) value; + return true; +} + const char * output_vec_const_move (rtx *operands) { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e01738127ed..0c269e4e8d9 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1177,6 +1177,30 @@ [(set_attr "type" "vecperm") (set_attr "length" "8")]) +(define_insn_and_split "*vspltisw_v2di_split" + [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") + (match_operand:V2DI 1 "vspltisw_vupkhsw_constant_split" "W"))] + "TARGET_P8_VECTOR && vspltisw_vupkhsw_constant_split (operands[1], V2DImode)" + "#" + "&& 1" + [(const_int 0)] +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = can_create_pseudo_p () + ? gen_reg_rtx (V4SImode) + : gen_lowpart (V4SImode, op0); + int value; + + vspltisw_vupkhsw_constant_p (op1, V2DImode, &value); + emit_insn (gen_altivec_vspltisw (tmp, GEN_INT (value))); + emit_insn (gen_altivec_vupkhsw_direct (op0, tmp)); + + DONE; +} + [(set_attr "type" "vecperm") + (set_attr "length" "8")]) + ;; Prefer using vector registers over GPRs. Prefer using ISA 3.0's XXSPLTISB ;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or diff --git a/gcc/testsuite/gcc.target/powerpc/pr104124.c b/gcc/testsuite/gcc.target/powerpc/pr104124.c new file mode 100644 index 00000000000..30e3b6f86eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr104124.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-final { scan-assembler {\mvspltisw\M} } } */ +/* { dg-final { scan-assembler {\mvupkhsw\M} } } */ +/* { dg-final { scan-assembler-not {\mlvx\M} } } */ + +#include + +vector unsigned long long +foo () +{ + return vec_splats ((unsigned long long) 12); +}