From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2078) id BA8413858D35; Thu, 29 Jun 2023 01:29:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BA8413858D35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688002153; bh=yQsKr+RFjvwWw3V5Iy3Js/iVU/i5ka/jvQpS8r9dEak=; h=From:To:Subject:Date:From; b=BRXwOveN8J0ExLsrkcN4ODeDTTxEN5GLsW2yxtW5ZjlzwZ8ijkt8+RUg/JSLmgEs4 +J1VkuDrKYR/em3mY09FjCWfPlr6grWh/SCR7jelRVtwqx8jjfcCK//MGdOCfE4J39 7rtBmUoswzEcgrAAJ+c+kJWBDOCuS6Vxv14LD/WU= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: hongtao Liu To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-7499] Refine maskloadmn pattern with UNSPEC_MASKLOAD. X-Act-Checkin: gcc X-Git-Author: liuhongt X-Git-Refname: refs/heads/releases/gcc-13 X-Git-Oldrev: e0f07bc97db9c84011fa97846f0b19a365d8ee48 X-Git-Newrev: ecc1af1f5b2c0fbcfa8840c79aa6102d413850b2 Message-Id: <20230629012913.BA8413858D35@sourceware.org> Date: Thu, 29 Jun 2023 01:29:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ecc1af1f5b2c0fbcfa8840c79aa6102d413850b2 commit r13-7499-gecc1af1f5b2c0fbcfa8840c79aa6102d413850b2 Author: liuhongt Date: Tue Jun 20 15:41:00 2023 +0800 Refine maskloadmn pattern with UNSPEC_MASKLOAD. If mem_addr points to a memory region with less than whole vector size bytes of accessible memory and k is a mask that would prevent reading the inaccessible bytes from mem_addr, add UNSPEC_MASKLOAD to prevent it to be transformed to vpblendd. gcc/ChangeLog: PR target/110309 * config/i386/sse.md (maskload): Refine pattern with UNSPEC_MASKLOAD. (maskload): Ditto. (*_load_mask): Extend mode iterator to VI12HFBF_AVX512VL. (*_load): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110309.c: New test. Diff: --- gcc/config/i386/sse.md | 32 ++++++++++++++++++-------------- gcc/testsuite/gcc.target/i386/pr110309.c | 10 ++++++++++ 2 files changed, 28 insertions(+), 14 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5be16e5551d..b504683cef3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1467,12 +1467,12 @@ }) (define_insn "*_load_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (unspec:VI12_AVX512VL - [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] + [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12HFBF_AVX512VL + (unspec:VI12HFBF_AVX512VL + [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand" "m")] UNSPEC_MASKLOAD) - (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C") + (match_operand:VI12HFBF_AVX512VL 2 "nonimm_or_0_operand" "0C") (match_operand: 3 "register_operand" "Yk")))] "TARGET_AVX512BW" "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" @@ -1481,9 +1481,9 @@ (set_attr "mode" "")]) (define_insn_and_split "*_load" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (unspec:VI12_AVX512VL - [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] + [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand" "=v") + (unspec:VI12HFBF_AVX512VL + [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand" "m")] UNSPEC_MASKLOAD))] "TARGET_AVX512BW" "#" @@ -26533,17 +26533,21 @@ "TARGET_AVX") (define_expand "maskload" - [(set (match_operand:V48H_AVX512VL 0 "register_operand") - (vec_merge:V48H_AVX512VL - (match_operand:V48H_AVX512VL 1 "memory_operand") + [(set (match_operand:V48_AVX512VL 0 "register_operand") + (vec_merge:V48_AVX512VL + (unspec:V48_AVX512VL + [(match_operand:V48_AVX512VL 1 "memory_operand")] + UNSPEC_MASKLOAD) (match_dup 0) (match_operand: 2 "register_operand")))] "TARGET_AVX512F") (define_expand "maskload" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "memory_operand") + [(set (match_operand:VI12HFBF_AVX512VL 0 "register_operand") + (vec_merge:VI12HFBF_AVX512VL + (unspec:VI12HFBF_AVX512VL + [(match_operand:VI12HFBF_AVX512VL 1 "memory_operand")] + UNSPEC_MASKLOAD) (match_dup 0) (match_operand: 2 "register_operand")))] "TARGET_AVX512BW") diff --git a/gcc/testsuite/gcc.target/i386/pr110309.c b/gcc/testsuite/gcc.target/i386/pr110309.c new file mode 100644 index 00000000000..f6e9e9c3c61 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110309.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 --param vect-partial-vector-usage=1 -march=znver4 -mprefer-vector-width=256" } */ +/* { dg-final { scan-assembler-not {(?n)vpblendd.*ymm} } } */ + + +void foo (int * __restrict a, int *b) +{ + for (int i = 0; i < 6; ++i) + a[i] = b[i] + 42; +}