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* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-12 1:50 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-12 1:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0efd3f3228b1d63391950fdd0f2b22a050b7848c
commit 0efd3f3228b1d63391950fdd0f2b22a050b7848c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jul 11 21:50:20 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 47 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3df157bf9d3..e77a2496b5f 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,44 @@
+==================== Branch work124, patch #20 ====================
+
+Optimize vec_extract of V4SF from memory with constant element numbers.
+
+This patch updates vec_extract of V4SF from memory with constant element
+numbers.
+
+I went through the alternatives, and I added alternatives to denote when we
+don't need to allocate a temporary base register. These cases include
+extracting element 0, and extracting elements 1-3 where we can use offsetable
+addresses.
+
+I added alternatives for power8 and power9 units to account for the expanded
+addressing on these machines (power8 can load SFmode into Altivec registers with
+x-form addressing, and power9 can use offsettable adressing to load up Altivec
+registers.
+
+This patch corrects the ISA test for loading SF values to altivec registers to
+be power8 vector, and not power7.
+
+This patch adds a combiner patch to combine loading up a SF element and
+converting it to double.
+
+It also removes the '?' from the 'r' constraint so that if the SFmode is needed
+in a GPR, it doesn't have to load it to the vector unit, store it, and then
+reload it into the GPR register.
+
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Fix ISA for loading
+ up SFmode values with x-form addresses. Remove ? from 'r' constraint.
+ Add more alternatives to prevent requiring a temporary base register if
+ we don't need the temporary.
+ (vsx_extract_v4sf_load_to_df): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-float-1.c: New file.
+
==================== Branch work124, patch #3 ====================
Fix typo in insn name.
@@ -8,7 +49,7 @@ In doing other work, I noticed that there was an insn:
Which did not have an iterator. I removed the useless <mode>.
-2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
@@ -28,7 +69,7 @@ This patch adds a new zero_extendditi2 insn which optimizes moving a GPR to a
vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to
load a 64-bit value into the bottom 64-bits of the vector register.
-2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
@@ -71,7 +112,7 @@ With this patch, GCC generates:
blr
-2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-13 22:47 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-13 22:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7afb3137794bac53c62fbfa837751663da210048
commit 7afb3137794bac53c62fbfa837751663da210048
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jul 13 18:47:43 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 6de12a5c853..23edbe5b6d4 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,41 @@
+==================== Branch work124, patch #25 ====================
+
+PR target/89213 - Optimize vector shift by a constant.
+
+Optimize vector shifts by a constant, taking advantage that the shift
+instructions only look at the bits within the element.
+
+The PowerPC doesn't have a VSPLTID instruction. This meant that if we are doing
+a V2DI shift of 0..15, we had to do VSPLTIW and VEXTSW2D instructions to load
+the constant into the vector register.
+
+Similarly for V4SI and V2DI, if we wanted to shift more than 15 bits, we would
+generate XXSPLTIB and VEXTSB2D or VEXTSB2W instructions to load the constant
+into the vector register.
+
+Given the vector shift instructions only look at the bottom 5 or 6 bits of the
+shift value, we can load the constant via VSPLTISW or XXSPLTIB instructions and
+eliminate the sign extend instructions (VEXTSW2D, VEXTSB2D, and VEXTSB2W).
+
+2023-07-13 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ PR target/89213
+ * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec.
+ (V4SI_V2DI): New mode iterator.
+ (vshift_code): New code iterator.
+ (altivec_<code>_const_<mode): New insns.
+ (altivec_shift_const_<mode>): New insns.
+ * config/rs6000/predicates.md (vector_shift_constant): New
+ predicate.
+
+gcc/testsuite/
+
+ PR target/89213
+ * gcc.target/powerpc/pr89213.c: New test.
+ * gcc.target/powerpc/vec-rlmi-rlnm.c: Update insn count.
+
==================== Branch work124, patch #24 ====================
Update fold-vec-extract insn counts on 32-bit big endian
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-13 6:09 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-13 6:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7a1d1d2131a694ad05368e0fd53236a567a0923b
commit 7a1d1d2131a694ad05368e0fd53236a567a0923b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jul 13 02:09:02 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1953f2cd1ce..6de12a5c853 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,25 @@
+==================== Branch work124, patch #24 ====================
+
+Update fold-vec-extract insn counts on 32-bit big endian
+
+In running tests, I noticed on big endian systems that the expected ADDIs is
+higher than the current number of ADDIs generated by the compiler. This patch
+adjusts those counts.
+
+2023-07-12 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/fold-vec-extract-char.p7.c: Update insn count for
+ 32-bit.
+ * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
+ * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
+
==================== Branch work124, patch #23 ====================
Allow constant element vec_extract to be converted to floating point
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-12 5:17 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-12 5:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:30a9d59811afc729b75f6580bc9d0cc33c467554
commit 30a9d59811afc729b75f6580bc9d0cc33c467554
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jul 12 01:17:01 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 6d6550dd547..1953f2cd1ce 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,34 @@
+==================== Branch work124, patch #23 ====================
+
+Allow constant element vec_extract to be converted to floating point
+
+This patch allows vec_extract of the following types to be converted to
+floating point by loading the value directly to the vector register, and then
+doing the conversion instead of loading the value to a GPR and then doing a
+direct move:
+
+vector int
+vector unsigned int
+vector unsigned short
+vector unsigned char
+
+2023-07-12 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000.md (fp_int_extend): New code attribute.
+ * config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
+ insn.
+ (vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-int_3.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
+
+
==================== Branch work124, patch #22 ====================
Add alternatives for vec_extract with constant element loading from memory.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-12 3:09 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-12 3:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:687a5384a18e8a77a3aa13b69e60b1aa0dcb70a4
commit 687a5384a18e8a77a3aa13b69e60b1aa0dcb70a4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jul 11 23:09:24 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 239643ae55e..6d6550dd547 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,40 @@
+==================== Branch work124, patch #22 ====================
+
+Add alternatives for vec_extract with constant element loading from memory.
+
+This patch expands the alternatives for doing vec_extract of V4SI, V8HI, and
+V16QI vectors with a constant offset when the vector is in memory. If the
+element number is 0 or we are using offsettable addressing for loading up GPR
+registers we don't need to allocate a temporary base register. We can fold the
+offset from the vec_extract into the normal address.
+
+I also added alternatives to load the values into vector registers. If we load
+the value into vector registers, we require X-form addressing.
+
+I added the VSX_EX_ISA mode attribute to distinguish that we can load 32-bit
+integers on a power8 system to vector registers, but we need a power9 system to
+be able to load 8-bit or 16-bit integers.
+
+In general, loading up small integer values with vec_extract into the vector
+registers explicitly is likely not done that much. However, this will be needed
+in later patches when we want to combine loading up a small integer value into a
+vector register with sign/zero extension. This happens when we want to do a
+vec_extract of a smal integer value and convert it to floating point.
+
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
+ (vsx_extract_<mode>_load): Add more alternatives for memory options.
+ Allow the load to load up vector registers if needed.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-char-1.c: New test.
+ * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+ * gcc.target/powerpc/vec-extract-mem-short-1.c: New test.
+
==================== Branch work124, patch #21 ====================
Optimize vec_extract of V4SF with variable element number being converted to DF
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-12 1:54 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-12 1:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:be66d3a901ebefc648b171c5cc5e92c69473709d
commit be66d3a901ebefc648b171c5cc5e92c69473709d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jul 11 21:54:31 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e77a2496b5f..239643ae55e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,27 @@
+==================== Branch work124, patch #21 ====================
+
+Optimize vec_extract of V4SF with variable element number being converted to DF
+
+This patch adds a combiner insn to include the conversion of float to double
+within the memory address when vec_extract of V4SF with a variable element
+number is done.
+
+It also removes the '?' from the 'r' constraint so that if the SFmode is needed
+in a GPR, it doesn't have to load it to the vector unit, store it on the stack,
+and reload it into a GPR register.
+
+2023-07-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Remove '?' from 'r'
+ constraint.
+ (vsx_extract_v4sf_var_load_to_df): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-float-2.c: New file.
+
==================== Branch work124, patch #20 ====================
Optimize vec_extract of V4SF from memory with constant element numbers.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner
@ 2023-07-07 19:53 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2023-07-07 19:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6ffc3b730a7c3177dd8e87d898824db8ba481b47
commit 6ffc3b730a7c3177dd8e87d898824db8ba481b47
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jul 7 15:53:30 2023 -0400
Update ChangeLog.meissner
Diff:
---
gcc/ChangeLog.meissner | 88 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3fc5794b8ec..3df157bf9d3 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,92 @@
+==================== Branch work124, patch #3 ====================
+
+Fix typo in insn name.
+
+In doing other work, I noticed that there was an insn:
+
+ vsx_extract_v4sf_<mode>_load
+
+Which did not have an iterator. I removed the useless <mode>.
+
+2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
+ vsx_extract_v4sf_<mode>_load.
+
+==================== Branch work124, patch #2 ====================
+
+Improve 64->128 bit zero extension on PowerPC (PR target/108958)
+
+If we are converting an unsigned DImode to a TImode value, and the TImode value
+will go in a vector register, GCC currently does the DImode to TImode conversion
+in GPR registers, and then moves the value to the vector register via a mtvsrdd
+instruction.
+
+This patch adds a new zero_extendditi2 insn which optimizes moving a GPR to a
+vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to
+load a 64-bit value into the bottom 64-bits of the vector register.
+
+2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ PR target/108958
+ * gcc/config/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+ PR target/108958
+ * gcc.target/powerpc/pr108958.c: New test.
+
+==================== Branch work124, patch #1 ====================
+
+Optimize vec_splats of vec_extract for V2DI/V2DF (PR target/99293)
+
+This patch optimizes cases like:
+
+ vector double v1, v2;
+ /* ... */
+ v2 = vec_splats (vec_extract (v1, 0); /* or */
+ v2 = vec_splats (vec_extract (v1, 1);
+
+Previously:
+
+ vector long long
+ splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+would generate:
+
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+With this patch, GCC generates:
+
+ xxpermdi 34,34,34,3
+ blr
+
+
+2023-07-07 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ PR target/99293
+ * gcc/config/rs6000/vsx.md (vsx_splat_extract_<mode>): New combiner
+ insn.
+
+gcc/testsuite/
+
+ PR target/108958
+ * gcc.target/powerpc/pr99293.c: New test.
+ * gcc.target/powerpc/builtins-1.c: Update insn count.
+
==================== Branch work124, baseline ====================
2023-07-06 Michael Meissner <meissner@linux.ibm.com>
Clone branch
-
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