From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 4355B3858D20; Wed, 12 Jul 2023 03:09:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4355B3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689131367; bh=9J/zanBH1P7GZicfl0OovyXJjwrU8XWiSgIgWA1W18w=; h=From:To:Subject:Date:From; b=iFv61dYHBAJhYgVIgk4gDffQ/w33mrhV0AgMULI3DHyTbVost6dbxi14v+eC4mixo DYu6sUMjWySc/3gEh8u5/3ooV6bjLOBHyAPouOMuC6KcJ8pKnhPHyoE8Q7k8a0Om0/ QXZU7gIaLeBg0Jr8S4Fid7keWXfQ5Hhq6G5+B5Ig= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work124 X-Git-Oldrev: 24ba160aa963e79ce3b6a60b7086d654e5f58f68 X-Git-Newrev: 687a5384a18e8a77a3aa13b69e60b1aa0dcb70a4 Message-Id: <20230712030927.4355B3858D20@sourceware.org> Date: Wed, 12 Jul 2023 03:09:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:687a5384a18e8a77a3aa13b69e60b1aa0dcb70a4 commit 687a5384a18e8a77a3aa13b69e60b1aa0dcb70a4 Author: Michael Meissner Date: Tue Jul 11 23:09:24 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 239643ae55e..6d6550dd547 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,40 @@ +==================== Branch work124, patch #22 ==================== + +Add alternatives for vec_extract with constant element loading from memory. + +This patch expands the alternatives for doing vec_extract of V4SI, V8HI, and +V16QI vectors with a constant offset when the vector is in memory. If the +element number is 0 or we are using offsettable addressing for loading up GPR +registers we don't need to allocate a temporary base register. We can fold the +offset from the vec_extract into the normal address. + +I also added alternatives to load the values into vector registers. If we load +the value into vector registers, we require X-form addressing. + +I added the VSX_EX_ISA mode attribute to distinguish that we can load 32-bit +integers on a power8 system to vector registers, but we need a power9 system to +be able to load 8-bit or 16-bit integers. + +In general, loading up small integer values with vec_extract into the vector +registers explicitly is likely not done that much. However, this will be needed +in later patches when we want to combine loading up a small integer value into a +vector register with sign/zero extension. This happens when we want to do a +vec_extract of a smal integer value and convert it to floating point. + +2023-07-11 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. + (vsx_extract__load): Add more alternatives for memory options. + Allow the load to load up vector registers if needed. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-char-1.c: New test. + * gcc.target/powerpc/vec-extract-mem-int-1.c: New test. + * gcc.target/powerpc/vec-extract-mem-short-1.c: New test. + ==================== Branch work124, patch #21 ==================== Optimize vec_extract of V4SF with variable element number being converted to DF