From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 76DB33858CDB; Thu, 13 Jul 2023 22:47:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 76DB33858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689288467; bh=XzBsLBpt9GyNg7RLb7JCCYJvqExKVonbYtbCXVcVdAE=; h=From:To:Subject:Date:From; b=Vc5+XPbrkiTN48eAGAq8A5X+WnOCx0uuZ025f8oQQZcQ/pt0fBB685Ofv6vCzlNgn UZ4cnPwibRqUoygB0Wyi8hUeB+JVHc8w8/MGDwaHFcpr82/na76/YkiDrn/KYbuhmn Zb7Fk2U7j2B+FtfH7HY+douEVMrtYtNX6WoFHyKc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work124)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work124 X-Git-Oldrev: 1b59a1dfaa000bb6127fe099bdc7822a46bf4b3e X-Git-Newrev: 7afb3137794bac53c62fbfa837751663da210048 Message-Id: <20230713224747.76DB33858CDB@sourceware.org> Date: Thu, 13 Jul 2023 22:47:47 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7afb3137794bac53c62fbfa837751663da210048 commit 7afb3137794bac53c62fbfa837751663da210048 Author: Michael Meissner Date: Thu Jul 13 18:47:43 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 6de12a5c853..23edbe5b6d4 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,41 @@ +==================== Branch work124, patch #25 ==================== + +PR target/89213 - Optimize vector shift by a constant. + +Optimize vector shifts by a constant, taking advantage that the shift +instructions only look at the bits within the element. + +The PowerPC doesn't have a VSPLTID instruction. This meant that if we are doing +a V2DI shift of 0..15, we had to do VSPLTIW and VEXTSW2D instructions to load +the constant into the vector register. + +Similarly for V4SI and V2DI, if we wanted to shift more than 15 bits, we would +generate XXSPLTIB and VEXTSB2D or VEXTSB2W instructions to load the constant +into the vector register. + +Given the vector shift instructions only look at the bottom 5 or 6 bits of the +shift value, we can load the constant via VSPLTISW or XXSPLTIB instructions and +eliminate the sign extend instructions (VEXTSW2D, VEXTSB2D, and VEXTSB2W). + +2023-07-13 Michael Meissner + +gcc/ + + PR target/89213 + * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec. + (V4SI_V2DI): New mode iterator. + (vshift_code): New code iterator. + (altivec__const_): New insns. + * config/rs6000/predicates.md (vector_shift_constant): New + predicate. + +gcc/testsuite/ + + PR target/89213 + * gcc.target/powerpc/pr89213.c: New test. + * gcc.target/powerpc/vec-rlmi-rlnm.c: Update insn count. + ==================== Branch work124, patch #24 ==================== Update fold-vec-extract insn counts on 32-bit big endian