From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 5CAD83858017; Fri, 14 Jul 2023 02:30:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5CAD83858017 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689301824; bh=o1yDCxMgi7qtolNQ9+ga33L5lbuTjf7I6ZdKVdeUvKM=; h=From:To:Subject:Date:From; b=b7sRuARAN9eR0D9a+uC2ha1kd6Xs/W7FzAraurN4dwWfLW2Lx07+yzg2l9UnelMsz q49pAkilRk1MJnfALYS0zagxM1r8c2u6CjCPfwntU94kG5rvqPlaFIFYsFcpztvRGK zXOwd+VKvOWjN/8SJwVYMzE44eDMuzVIWerVuzBA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add auto-vectorization compile option for RVV X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 98134b3c4d24478e00c45389a8ca6a663f4bcbba X-Git-Newrev: 034f133b4a882536d76232bf66107aa7cfd40c7b Message-Id: <20230714023024.5CAD83858017@sourceware.org> Date: Fri, 14 Jul 2023 02:30:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:034f133b4a882536d76232bf66107aa7cfd40c7b commit 034f133b4a882536d76232bf66107aa7cfd40c7b Author: Ju-Zhe Zhong Date: Tue Apr 25 21:05:54 2023 -0600 RISC-V: Add auto-vectorization compile option for RVV This patch is adding 2 compile option for RVV auto-vectorization. 1. -param=riscv-autovec-preference= This option is to specify the auto-vectorization approach for RVV. Currently, we only support scalable and fixed-vlmax. - scalable means VLA auto-vectorization. The vector-length to compiler is unknown and runtime invariant. Such approach can allow us compile the code run on any vector-length RVV CPU. - fixed-vlmax means the compile known the RVV CPU vector-length, compile option in fixed-length VLS auto-vectorization. Meaning if we specify vector-length=512. The execution file can only run on vector-length = 512 RVV CPU. - TODO: we may need to support min-length VLS auto-vectorization, means the execution file can run on larger length RVV CPU. 2. -param=riscv-autovec-lmul= Specify LMUL choosing for RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add enum for auto-vectorization preference. (enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV auto-vectorization. * config/riscv/riscv.opt: Add compile option for RVV auto-vectorization. Diff: --- gcc/config/riscv/riscv-opts.h | 16 ++++++++++++++++ gcc/config/riscv/riscv.opt | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index be8de182312..59449c5de8d 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,7 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; + enum riscv_multilib_select_kind { /* Select multilib by builtin way. */ select_by_builtin, @@ -76,6 +77,21 @@ enum riscv_multilib_select_kind { select_by_abi, }; +/* RISC-V auto-vectorization preference. */ +enum riscv_autovec_preference_enum { + NO_AUTOVEC, + RVV_SCALABLE, + RVV_FIXED_VLMAX +}; + +/* RISC-V auto-vectorization RVV LMUL. */ +enum riscv_autovec_lmul_enum { + RVV_M1 = 1, + RVV_M2 = 2, + RVV_M4 = 4, + RVV_M8 = 8 +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index bc5e63ab3e6..63d4710cb15 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -258,3 +258,40 @@ Set the version of RISC-V ISA spec. minline-atomics Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1) Always inline subword atomic operations. + +Enum +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum) +The RISC-V auto-vectorization preference: + +EnumValue +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC) + +EnumValue +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE) + +EnumValue +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX) + +-param=riscv-autovec-preference= +Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(NO_AUTOVEC) +-param=riscv-autovec-preference= Set the preference of auto-vectorization in the RISC-V port. + +Enum +Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) +The RVV possible LMUL: + +EnumValue +Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1) + +EnumValue +Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2) + +EnumValue +Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4) + +EnumValue +Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8) + +-param=riscv-autovec-lmul= +Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1) +-param=riscv-autovec-lmul= Set the RVV LMUL of auto-vectorization in the RISC-V port.