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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Eliminate AMO op fences
@ 2023-07-14 2:32 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6065f5d6f76b79409bae6d2ff1ad14ee7a2f90fb
commit 6065f5d6f76b79409bae6d2ff1ad14ee7a2f90fb
Author: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed Apr 5 09:48:06 2023 -0700
RISC-V: Eliminate AMO op fences
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_memmodel_needs_amo_release): Change function name.
(riscv_print_operand): Remove unneeded %F case.
* config/riscv/sync.md: Remove unneeded fences.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diff:
---
gcc/config/riscv/riscv.cc | 16 +++++-----------
gcc/config/riscv/sync.md | 12 ++++++------
2 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 13661c54fa8..b6b00be0dca 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4317,11 +4317,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
}
}
-/* Return true if a FENCE should be emitted to before a memory access to
- implement the release portion of memory model MODEL. */
+/* Return true if the .RL suffix should be added to an AMO to implement the
+ release portion of memory model MODEL. */
static bool
-riscv_memmodel_needs_release_fence (enum memmodel model)
+riscv_memmodel_needs_amo_release (enum memmodel model)
{
switch (model)
{
@@ -4347,7 +4347,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
- 'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -4509,19 +4508,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
case 'A':
if (riscv_memmodel_needs_amo_acquire (model)
- && riscv_memmodel_needs_release_fence (model))
+ && riscv_memmodel_needs_amo_release (model))
fputs (".aqrl", file);
else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
- else if (riscv_memmodel_needs_release_fence (model))
+ else if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
break;
- case 'F':
- if (riscv_memmodel_needs_release_fence (model))
- fputs ("fence iorw,ow; ", file);
- break;
-
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 1acb78a9ae4..9a3b57bd09f 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -91,9 +91,9 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
+ "amo<insn>.<amo>%A2\tzero,%z1,%0"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_fetch_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -105,9 +105,9 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
+ "amo<insn>.<amo>%A3\t%0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
@@ -247,9 +247,9 @@
(set (match_dup 1)
(match_operand:GPR 2 "register_operand" "0"))]
"TARGET_ATOMIC"
- "%F3amoswap.<amo>%A3 %0,%z2,%1"
+ "amoswap.<amo>%A3\t%0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_expand "atomic_exchange<mode>"
[(match_operand:SHORT 0 "register_operand") ;; old value at mem
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Eliminate AMO op fences
@ 2023-05-25 23:16 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-05-25 23:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:52831399ab4553b3e7487c73b7c5a39a3254c80c
commit 52831399ab4553b3e7487c73b7c5a39a3254c80c
Author: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed Apr 5 09:48:06 2023 -0700
RISC-V: Eliminate AMO op fences
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_memmodel_needs_amo_release): Change function name.
(riscv_print_operand): Remove unneeded %F case.
* config/riscv/sync.md: Remove unneeded fences.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diff:
---
gcc/config/riscv/riscv.cc | 16 +++++-----------
gcc/config/riscv/sync.md | 12 ++++++------
2 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f8bc402e35a..ce79c9bf123 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4317,11 +4317,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
}
}
-/* Return true if a FENCE should be emitted to before a memory access to
- implement the release portion of memory model MODEL. */
+/* Return true if the .RL suffix should be added to an AMO to implement the
+ release portion of memory model MODEL. */
static bool
-riscv_memmodel_needs_release_fence (enum memmodel model)
+riscv_memmodel_needs_amo_release (enum memmodel model)
{
switch (model)
{
@@ -4347,7 +4347,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
- 'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -4509,19 +4508,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
case 'A':
if (riscv_memmodel_needs_amo_acquire (model)
- && riscv_memmodel_needs_release_fence (model))
+ && riscv_memmodel_needs_amo_release (model))
fputs (".aqrl", file);
else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
- else if (riscv_memmodel_needs_release_fence (model))
+ else if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
break;
- case 'F':
- if (riscv_memmodel_needs_release_fence (model))
- fputs ("fence iorw,ow; ", file);
- break;
-
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 1acb78a9ae4..9a3b57bd09f 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -91,9 +91,9 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
+ "amo<insn>.<amo>%A2\tzero,%z1,%0"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_fetch_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -105,9 +105,9 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
+ "amo<insn>.<amo>%A3\t%0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
@@ -247,9 +247,9 @@
(set (match_dup 1)
(match_operand:GPR 2 "register_operand" "0"))]
"TARGET_ATOMIC"
- "%F3amoswap.<amo>%A3 %0,%z2,%1"
+ "amoswap.<amo>%A3\t%0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_expand "atomic_exchange<mode>"
[(match_operand:SHORT 0 "register_operand") ;; old value at mem
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-05-25 23:16 Jeff Law
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