From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 791C6385773C; Fri, 14 Jul 2023 02:34:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 791C6385773C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302093; bh=59nw8UEfEKrJqSezoTggNlWdTiA5YRN2FhAcV7udeRk=; h=From:To:Subject:Date:From; b=hrNy8GqFRik/JdSD59v4UlZC9TDbeJX1H8KLbiI6USrW1mu0dO3HnkaCocxnlJgGK L5fEqu9FKgrWeFPrJeSFHBJqFAtsi+EmVxUBi3sJXW72ZFUvoN661onEEmpHhfGp2r 0NA1BmfHT8tnohAuGZRowOl91Pz1CHW8e3Ib7fBE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Split off shift patterns for autovectorization. X-Act-Checkin: gcc X-Git-Author: Robin Dapp X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 9f2ba20cf726ae96ef49fd8c25e2416184ffb5d8 X-Git-Newrev: 1315e9a2ea36f274c07e1ce07fea70890a7ebca6 Message-Id: <20230714023453.791C6385773C@sourceware.org> Date: Fri, 14 Jul 2023 02:34:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1315e9a2ea36f274c07e1ce07fea70890a7ebca6 commit 1315e9a2ea36f274c07e1ce07fea70890a7ebca6 Author: Robin Dapp Date: Wed May 10 09:52:43 2023 +0200 RISC-V: Split off shift patterns for autovectorization. This patch splits off the shift patterns of the binop patterns. This is necessary as the scalar shifts require a Pmode operand as shift count. To this end, a new iterator any_int_binop_no_shift is introduced. At a later point when the binops are split up further in commutative and non-commutative patterns (which both do not include the shift patterns) we might not need this anymore. gcc/ChangeLog: * config/riscv/autovec.md (3): Add scalar shift pattern. (v3): Add vector shift pattern. * config/riscv/vector-iterators.md: New iterator. Diff: --- gcc/config/riscv/autovec.md | 47 +++++++++++++++++++++++++++++++++++- gcc/config/riscv/vector-iterators.md | 4 +++ 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 58926ed3e67..ac0c939d277 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -97,7 +97,7 @@ (define_expand "3" [(set (match_operand:VI 0 "register_operand") - (any_int_binop:VI + (any_int_binop_no_shift:VI (match_operand:VI 1 "") (match_operand:VI 2 "")))] "TARGET_VECTOR" @@ -119,3 +119,48 @@ NULL, mode); DONE; }) + +;; ------------------------------------------------------------------------- +;; ---- [INT] Binary shifts by scalar. +;; ------------------------------------------------------------------------- +;; Includes: +;; - vsll.vx/vsra.vx/vsrl.vx +;; - vsll.vi/vsra.vi/vsrl.vi +;; ------------------------------------------------------------------------- + +(define_expand "3" + [(set (match_operand:VI 0 "register_operand") + (any_shift:VI + (match_operand:VI 1 "register_operand") + (match_operand: 2 "csr_operand")))] + "TARGET_VECTOR" +{ + if (!CONST_SCALAR_INT_P (operands[2])) + operands[2] = gen_lowpart (Pmode, operands[2]); + riscv_vector::emit_len_binop (code_for_pred_scalar + (, mode), + operands[0], operands[1], operands[2], + NULL_RTX, mode, Pmode); + DONE; +}) + +;; ------------------------------------------------------------------------- +;; ---- [INT] Binary shifts by scalar. +;; ------------------------------------------------------------------------- +;; Includes: +;; - vsll.vv/vsra.vv/vsrl.vv +;; ------------------------------------------------------------------------- + +(define_expand "v3" + [(set (match_operand:VI 0 "register_operand") + (any_shift:VI + (match_operand:VI 1 "register_operand") + (match_operand:VI 2 "vector_shift_operand")))] + "TARGET_VECTOR" +{ + riscv_vector::emit_len_binop (code_for_pred + (, mode), + operands[0], operands[1], operands[2], + NULL_RTX, mode); + DONE; +}) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 29c9d77674b..5cf958ba845 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1409,6 +1409,10 @@ (define_code_iterator any_non_commutative_binop [minus div udiv mod umod]) +(define_code_iterator any_int_binop_no_shift + [plus minus and ior xor smax umax smin umin mult div udiv mod umod +]) + (define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus]) (define_code_iterator sat_int_plus_binop [ss_plus us_plus]) (define_code_iterator sat_int_minus_binop [ss_minus us_minus])