[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] OPTABS: Extend the number of expanding instructions pattern

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] OPTABS: Extend the number of expanding instructions pattern

[Jeff Law]

https://gcc.gnu.org/g:34036d352b034ed0212c473ba2e4235237b05300

commit 34036d352b034ed0212c473ba2e4235237b05300
Author: Pan Li <pan2.li@intel.com>
Date:   Mon May 15 22:05:44 2023 +0800

    OPTABS: Extend the number of expanding instructions pattern
    
    We (RVV) is going to add a rounding mode operand into floating-point
    instructions which have 11 operands.
    
    Since we are going have intrinsic that is adding rounding mode argument:
    https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
    
    This is the patch that is adding rounding mode operand in RISC-V port:
    https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
    You can see there are 11 operands in these patterns.
    
    gcc/ChangeLog:
    
            * optabs.cc (maybe_gen_insn): Add case to generate instruction
            that has 11 operands.
    
    Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Diff:
---
 gcc/optabs.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index c8e39c82d57..a12333c7169 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
 			      ops[3].value, ops[4].value, ops[5].value,
 			      ops[6].value, ops[7].value, ops[8].value,
 			      ops[9].value);
+    case 11:
+      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
+			      ops[3].value, ops[4].value, ops[5].value,
+			      ops[6].value, ops[7].value, ops[8].value,
+			      ops[9].value, ops[10].value);
     }
   gcc_unreachable ();
 }

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] OPTABS: Extend the number of expanding instructions pattern

[Jeff Law]

https://gcc.gnu.org/g:88c4a014b60f5317ccbbe4299039b6e7b5c43dc7

commit 88c4a014b60f5317ccbbe4299039b6e7b5c43dc7
Author: Pan Li <pan2.li@intel.com>
Date:   Mon May 15 22:05:44 2023 +0800

    OPTABS: Extend the number of expanding instructions pattern
    
    We (RVV) is going to add a rounding mode operand into floating-point
    instructions which have 11 operands.
    
    Since we are going have intrinsic that is adding rounding mode argument:
    https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
    
    This is the patch that is adding rounding mode operand in RISC-V port:
    https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
    You can see there are 11 operands in these patterns.
    
    gcc/ChangeLog:
    
            * optabs.cc (maybe_gen_insn): Add case to generate instruction
            that has 11 operands.
    
    Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Diff:
---
 gcc/optabs.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index c8e39c82d57..a12333c7169 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
 			      ops[3].value, ops[4].value, ops[5].value,
 			      ops[6].value, ops[7].value, ops[8].value,
 			      ops[9].value);
+    case 11:
+      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
+			      ops[3].value, ops[4].value, ops[5].value,
+			      ops[6].value, ops[7].value, ops[8].value,
+			      ops[9].value, ops[10].value);
     }
   gcc_unreachable ();
 }