[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Allow more loading of const vectors.

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Allow more loading of const vectors.

[Jeff Law]

https://gcc.gnu.org/g:280318113e45000d50f159ea9f97385d583c1f49

commit 280318113e45000d50f159ea9f97385d583c1f49
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Fri May 12 10:26:51 2023 +0200

    RISC-V: Allow more loading of const vectors.
    
    This patch fixes the recent vmv patch in order to allow loading
    of constants via vmv.vi with the "fixed-vlmax" vectorization flavor.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_const_insns): Remove else.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: New test.
            * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: New test.

Diff:
---
 gcc/config/riscv/riscv.cc                                       | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 6 ++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 6 ++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8e3dd67632f..02f9396c22c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x)
 	   The Wc0, Wc1 constraints are already covered by the
 	   vi constraint so we do not need to check them here
 	   separately.  */
-	else if (TARGET_VECTOR && satisfies_constraint_vi (x))
+	if (TARGET_VECTOR && satisfies_constraint_vi (x))
 	  return 1;
 
 	/* TODO: We may support more const vector in the future.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
new file mode 100644
index 00000000000..631ea3bf268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
new file mode 100644
index 00000000000..7ded6cc18d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Allow more loading of const vectors.

[Jeff Law]

https://gcc.gnu.org/g:9ceaf99deedfa32c9a7e8a642e187705b645cc48

commit 9ceaf99deedfa32c9a7e8a642e187705b645cc48
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Fri May 12 10:26:51 2023 +0200

    RISC-V: Allow more loading of const vectors.
    
    This patch fixes the recent vmv patch in order to allow loading
    of constants via vmv.vi with the "fixed-vlmax" vectorization flavor.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_const_insns): Remove else.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: New test.
            * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: New test.

Diff:
---
 gcc/config/riscv/riscv.cc                                       | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 6 ++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 6 ++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 235be758c03..8320069f92f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x)
 	   The Wc0, Wc1 constraints are already covered by the
 	   vi constraint so we do not need to check them here
 	   separately.  */
-	else if (TARGET_VECTOR && satisfies_constraint_vi (x))
+	if (TARGET_VECTOR && satisfies_constraint_vi (x))
 	  return 1;
 
 	/* TODO: We may support more const vector in the future.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
new file mode 100644
index 00000000000..631ea3bf268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
new file mode 100644
index 00000000000..7ded6cc18d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */