From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id EE7503858C66; Fri, 14 Jul 2023 02:38:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EE7503858C66 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302316; bh=KSoH4r8hNZybv3CQ9MsqGZUItLf74A05GWEDHyOqFIc=; h=From:To:Subject:Date:From; b=oflpomClpzInjiNjGgvIo+z436bMRQYse3GKsLiHy6OQNDyB/ae67KFJT2ZdnJhUw 3f7TKoaWEKCZYD+uJLn/aiIVpuV/ZFQULmOIufa/1KlWFb7uFPD02V2Shb5Qhr3fgY wgQAk6rZ3S1cBXivvQV4fuV3BuP5AgEApEkHmQu8= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix incorrect code of reaching inaccessible memory address X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 023c974e8ffc14f4bf83fb88a41b009f19090201 X-Git-Newrev: 41467d6f7b18432541a6cdac22350ccdd31a3824 Message-Id: <20230714023836.EE7503858C66@sourceware.org> Date: Fri, 14 Jul 2023 02:38:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:41467d6f7b18432541a6cdac22350ccdd31a3824 commit 41467d6f7b18432541a6cdac22350ccdd31a3824 Author: Juzhe-Zhong Date: Wed May 24 10:59:02 2023 +0800 RISC-V: Fix incorrect code of reaching inaccessible memory address To fix this issue, we seperate Vl operand and normal operands. gcc/ChangeLog: * config/riscv/autovec.md: Adjust for new interface. * config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand. (emit_nonvlmax_insn): Add AVL operand. * config/riscv/riscv-v.cc (emit_vlmax_insn): Add VL operand. (emit_nonvlmax_insn): Add AVL operand. (sew64_scalar_helper): Adjust for new interface. (expand_tuple_move): Ditto. * config/riscv/vector.md: Ditto. Signed-off-by: Juzhe-Zhong Diff: --- gcc/config/riscv/autovec.md | 4 ++-- gcc/config/riscv/riscv-protos.h | 4 ++-- gcc/config/riscv/riscv-v.cc | 30 +++++++++++++++++++----------- gcc/config/riscv/vector.md | 4 ++-- 4 files changed, 25 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 04b4459222a..7c87b6012f6 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -32,7 +32,7 @@ "TARGET_VECTOR" { riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, operands); + riscv_vector::RVV_UNOP, operands, operands[2]); DONE; }) @@ -44,7 +44,7 @@ "TARGET_VECTOR" { riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, operands); + riscv_vector::RVV_UNOP, operands, operands[2]); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0ae4656befb..159b51a1210 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -172,8 +172,8 @@ bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); bool legitimize_move (rtx, rtx); void emit_vlmax_vsetvl (machine_mode, rtx); void emit_hard_vlmax_vsetvl (machine_mode, rtx); -void emit_vlmax_insn (unsigned, int, rtx *); -void emit_nonvlmax_insn (unsigned, int, rtx *); +void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0); +void emit_nonvlmax_insn (unsigned, int, rtx *, rtx); enum vlmul_type get_vlmul (machine_mode); unsigned int get_ratio (machine_mode); unsigned int get_nf (machine_mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index fa61a850a22..1cdc4a99701 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -71,7 +71,8 @@ public: m_fully_unmasked_p (false), m_use_real_merge_p (false), m_needs_avl_p (false), m_vlmax_p (false), m_has_tail_policy_p (false), m_has_mask_policy_p (false), m_tail_policy (TAIL_ANY), - m_mask_policy (MASK_ANY), m_dest_mode (VOIDmode), m_mask_mode (VOIDmode) + m_mask_policy (MASK_ANY), m_dest_mode (VOIDmode), m_mask_mode (VOIDmode), + m_vl_op (NULL_RTX) {} /* Initializer for various configurations. */ @@ -83,7 +84,8 @@ public: m_use_real_merge_p (use_real_merge_p), m_needs_avl_p (needs_avl_p), m_vlmax_p (vlmax_p), m_has_tail_policy_p (false), m_has_mask_policy_p (false), m_tail_policy (TAIL_ANY), - m_mask_policy (MASK_ANY), m_dest_mode (dest_mode), m_mask_mode (mask_mode) + m_mask_policy (MASK_ANY), m_dest_mode (dest_mode), + m_mask_mode (mask_mode), m_vl_op (NULL_RTX) {} void set_policy (enum tail_policy ta) @@ -96,6 +98,7 @@ public: m_has_mask_policy_p = true; m_mask_policy = ma; } + void set_vl (rtx vl) { m_vl_op = vl; } void add_output_operand (rtx x, machine_mode mode) { @@ -169,7 +172,7 @@ public: if (m_needs_avl_p) { - rtx len = ops[m_op_num]; + rtx len = m_vl_op; if (m_vlmax_p) { if (const_vlmax_p (m_dest_mode)) @@ -228,6 +231,7 @@ private: enum mask_policy m_mask_policy; machine_mode m_dest_mode; machine_mode m_mask_mode; + rtx m_vl_op; expand_operand m_ops[MAX_OPERANDS]; }; @@ -339,7 +343,7 @@ autovec_use_vlmax_p (void) /* This function emits a {VLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the * actual operation. */ void -emit_vlmax_insn (unsigned icode, int op_num, rtx *ops) +emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) { machine_mode data_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (data_mode).require (); @@ -352,13 +356,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops) /*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode); e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); + /* According to LRA mov pattern in vector.md, we have a clobber operand + to be used ad VL operand. */ + e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); } /* This function emits a {NONVLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the * actual operation. */ void -emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops) +emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl) { machine_mode data_mode = GET_MODE (ops[0]); machine_mode mask_mode = get_mask_mode (data_mode).require (); @@ -371,6 +378,7 @@ emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops) /*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode); e.set_policy (TAIL_ANY); e.set_policy (MASK_ANY); + e.set_vl (avl); e.emit_insn ((enum insn_code) icode, ops); } @@ -810,9 +818,9 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, *scalar_op = force_reg (scalar_mode, *scalar_op); rtx tmp = gen_reg_rtx (vector_mode); - rtx ops[] = {tmp, *scalar_op, vl}; + rtx ops[] = {tmp, *scalar_op}; riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), - riscv_vector::RVV_UNOP, ops); + riscv_vector::RVV_UNOP, ops, vl); emit_vector_func (operands, tmp); return true; @@ -1119,9 +1127,9 @@ expand_tuple_move (rtx *ops) if (fractional_p) { - rtx operands[] = {subreg, mem, ops[4]}; + rtx operands[] = {subreg, mem}; emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, - operands); + operands, ops[4]); } else emit_move_insn (subreg, mem); @@ -1144,9 +1152,9 @@ expand_tuple_move (rtx *ops) if (fractional_p) { - rtx operands[] = {mem, subreg, ops[4]}; + rtx operands[] = {mem, subreg}; emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, - operands); + operands, ops[4]); } else emit_move_insn (mem, subreg); diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 8a95dbfaac2..39acdfb8408 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -761,7 +761,7 @@ { riscv_vector::emit_vlmax_vsetvl (mode, operands[2]); riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, operands); + riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; }) @@ -781,7 +781,7 @@ { riscv_vector::emit_vlmax_vsetvl (mode, operands[2]); riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, operands); + riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; })