[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfncvt.rod instruction

[Jeff Law <law@gcc.gnu.org>]

https://gcc.gnu.org/g:6267bf06f7b6533fc5c840d0a873b63818b11b25

commit 6267bf06f7b6533fc5c840d0a873b63818b11b25
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed May 31 18:47:03 2023 +0800

    RISC-V: Remove FRM for vfncvt.rod instruction
    
    Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Remove FRM.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cd696da5d89..60f052bcec9 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7290,10 +7290,8 @@
 	     (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
-	     (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:<V_DOUBLE_TRUNC>
 	    [(float_truncate:<V_DOUBLE_TRUNC>
 	       (match_operand:VWEXTF 3 "register_operand"          "  0,  0,  0,  0,   vr,   vr"))] UNSPEC_ROD)