From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 3B33E38582B7; Fri, 14 Jul 2023 02:41:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3B33E38582B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302469; bh=OKlzl/rV7mttbUWMtmKiRzgLazu6BrbajLHf2DW5F1w=; h=From:To:Subject:Date:From; b=CMh4Ttcdni7cFkpwdGHDTtTJIeJ7jK3Ps76SdWyDoHBVj8z2ifHnwWtI9992BDJCy LYyuOw1I99hRV7MQHI0X/61SxZrtedvsYEwfyWzU4/J9AK/J+f7esc4LlmOpcfXysb Xbr5H8TerCK6RgNjDHoUqamuVjiIcHN7LtpAvNoo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to float widening conversion) X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 6267bf06f7b6533fc5c840d0a873b63818b11b25 X-Git-Newrev: 758c6e9614cc7bce13c7681fa38930b00bb410dd Message-Id: <20230714024109.3B33E38582B7@sourceware.org> Date: Fri, 14 Jul 2023 02:41:09 +0000 (GMT) List-Id: https://gcc.gnu.org/g:758c6e9614cc7bce13c7681fa38930b00bb410dd commit 758c6e9614cc7bce13c7681fa38930b00bb410dd Author: Juzhe-Zhong Date: Wed May 31 18:43:44 2023 +0800 RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to float widening conversion) Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt.f.x.v doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li Diff: --- gcc/config/riscv/vector.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 60f052bcec9..cb4e77e7854 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7159,10 +7159,8 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]