From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 74A873857732; Fri, 14 Jul 2023 02:45:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 74A873857732 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302738; bh=iW6BhTBqeJ/KA164yl9JhrYpNjGrkJLPvJDXdhioC7U=; h=From:To:Subject:Date:From; b=UrZlUYDZs0674foJOKtqQ1RSnX2KHDkCScZU1BLUIBfQhqSsqBpO32WEAknlQ5w3X s9B/ypFe1+y7l1X/WKC0LS0+ZTPHjWMQAFw5OpFNRB48NrS4AqB9bnsUh6sC1AxGyl Z4lDU4a86ykJcUrljpQP4wyPUNa4yCc/8U2KikSk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one typo in full-vec-movel test X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 27ec8bbc266432fe7ccc34a7b53ffd3692311f81 X-Git-Newrev: 792ffe336f14623e10002dedaf5cd0d80846404e Message-Id: <20230714024538.74A873857732@sourceware.org> Date: Fri, 14 Jul 2023 02:45:38 +0000 (GMT) List-Id: https://gcc.gnu.org/g:792ffe336f14623e10002dedaf5cd0d80846404e commit 792ffe336f14623e10002dedaf5cd0d80846404e Author: Pan Li Date: Tue Jun 13 15:13:48 2023 +0800 RISC-V: Fix one typo in full-vec-movel test This patch would like to fix one typo when checking assembly of full-vec-movel. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Adjust dg-do to comiple for asm checking. Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index c1119cddee7..c32c31ecd69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do compile } */ /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include