From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 04D61385828E; Fri, 14 Jul 2023 02:46:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 04D61385828E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302774; bh=F1tz3fKhwqpUvFtHa3fLHiBnmS6azz2wAJgFaOzfLfU=; h=From:To:Subject:Date:From; b=gRkD0kGbUsnaXsnVtrxLr/vVPLgdrRSS8xQ6C6w3sndl9jTnUpUMaZrUVBcDZOgSe cvYgtQzkj15KfGjGj5vstiJMRMpbcFWQdQkg+WCD2spFeUBqzJulYva+jY6aiLXkPX xATLxgiPTqF0daACl3SrGM0bktjGQfSfZlHRcguE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Align the predictor style for define_insn_and_split X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 17091f4b5064517a76f86d8950823ca43861bad3 X-Git-Newrev: 65c6d6d2193a90485c81d6391a532a03b5301753 Message-Id: <20230714024614.04D61385828E@sourceware.org> Date: Fri, 14 Jul 2023 02:46:14 +0000 (GMT) List-Id: https://gcc.gnu.org/g:65c6d6d2193a90485c81d6391a532a03b5301753 commit 65c6d6d2193a90485c81d6391a532a03b5301753 Author: Pan Li Date: Wed Jun 14 10:10:44 2023 +0800 RISC-V: Align the predictor style for define_insn_and_split This patch is considered as the follow up of the below PATCH. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html We aligned the predictor style for the define_insn_and_split suggested by Kito. To avoid potential issues before we hit. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-opt.md: Align the predictor sytle. * config/riscv/autovec.md: Ditto. Diff: --- gcc/config/riscv/autovec-opt.md | 20 ++++++++++---------- gcc/config/riscv/autovec.md | 24 ++++++++++++------------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index aef28e445e1..fb1b07205aa 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -37,9 +37,9 @@ (match_operand: 4 "register_operand" " vr, vr")) (match_operand:VWEXTI 3 "register_operand" " vr, vr")) (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (, mode); @@ -132,9 +132,9 @@ (bitmanip_bitwise:VB (not:VB (match_operand:VB 2 "register_operand" " vr")) (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (, mode); @@ -159,9 +159,9 @@ (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_n (, mode); @@ -346,9 +346,9 @@ (match_operand:VWEXTI 1 "register_operand" " vr,vr") (any_extend:VWEXTI (match_operand: 2 "vector_shift_operand" " vr,vk")))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_narrow (, mode); @@ -364,9 +364,9 @@ (any_shiftrt:VWEXTI (match_operand:VWEXTI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index eadc2c5b595..c23a625afe1 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -155,9 +155,9 @@ (any_shift:VI (match_operand:VI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); @@ -180,9 +180,9 @@ (any_shift:VI (match_operand:VI 1 "register_operand" " vr,vr") (match_operand:VI 2 "vector_shift_operand" " vr,vk")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { riscv_vector::emit_vlmax_insn (code_for_pred (, mode), @@ -205,9 +205,9 @@ [(set (match_operand:VB 0 "register_operand" "=vr") (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred (, mode); @@ -227,9 +227,9 @@ (define_insn_and_split "one_cmpl2" [(set (match_operand:VB 0 "register_operand" "=vr") (not:VB (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (mode); @@ -366,9 +366,9 @@ [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") (any_extend:VWEXTI (match_operand: 1 "register_operand" "vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (, mode); @@ -409,9 +409,9 @@ [(set (match_operand: 0 "register_operand" "=vr") (truncate: (match_operand:VWEXTI 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_trunc (mode);