From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id C7D533857C44; Fri, 14 Jul 2023 02:47:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C7D533857C44 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689302824; bh=ci9LTcrvE54ZoHYLZltHx3+u2vRKmzG4LpchX36oA6k=; h=From:To:Subject:Date:From; b=E7QYkMF9SfHg2AU37AgnZegqUYpBOpGDHH10Q/ZNoMFPjpBvO7Pwp1dymz7LspMF5 IH32tUqzOuTiihREMiiCzwBHT9US1UXAIXUyEBYf5V/ceuaq+13qMRo9xQvuuwBGNA x4sYN3AeGBqT/qdSa12T9YxjQDogn+SjfRF4nme4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add sign-extending variants for vmv.x.s. X-Act-Checkin: gcc X-Git-Author: Robin Dapp X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 487008451ff78d7bac8963743dfdcfda655a2639 X-Git-Newrev: cb54ac3f17408662a910411b76da70a4c9d71042 Message-Id: <20230714024704.C7D533857C44@sourceware.org> Date: Fri, 14 Jul 2023 02:47:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:cb54ac3f17408662a910411b76da70a4c9d71042 commit cb54ac3f17408662a910411b76da70a4c9d71042 Author: Robin Dapp Date: Mon Jun 5 13:12:01 2023 +0200 RISC-V: Add sign-extending variants for vmv.x.s. When the destination register of a vmv.x.s needs to be sign extended to XLEN we currently emit an sext insn. Since vmv.x.s performs this automatically this patch adds two instruction patterns that include sign_extend for the destination operand. gcc/ChangeLog: * config/riscv/vector-iterators.md: Add VI_QH iterator. * config/riscv/autovec-opt.md (@pred_extract_first_sextdi): New vmv.x.s pattern that includes sign extension. (@pred_extract_first_sextsi): Dito for SImode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ensure that no sext insns are present. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito. Diff: --- gcc/config/riscv/autovec-opt.md | 29 ++++++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 5 ++++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-1.c | 2 ++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-2.c | 2 ++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-3.c | 2 ++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-4.c | 2 ++ 6 files changed, 42 insertions(+) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index fb1b07205aa..28040805b23 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -376,3 +376,32 @@ } [(set_attr "type" "vnshift") (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- Sign-extension for vmv.x.s. +;; ------------------------------------------------------------------------- +(define_insn "*pred_extract_first_sextdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (unspec: + [(vec_select: + (match_operand:VI_QHS 1 "register_operand""vr") + (parallel [(const_int 0)])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] + "TARGET_VECTOR && Pmode == DImode" + "vmv.x.s\t%0,%1" + [(set_attr "type" "vimovvx") + (set_attr "mode" "")]) + +(define_insn "*pred_extract_first_sextsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI + (unspec: + [(vec_select: + (match_operand:VI_QH 1 "register_operand" "vr") + (parallel [(const_int 0)])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] + "TARGET_VECTOR && Pmode == SImode" + "vmv.x.s\t%0,%1" + [(set_attr "type" "vimovvx") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a5a660e2403..1e35fb18b5d 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -352,6 +352,11 @@ (VNx2DI "TARGET_FULL_V") (VNx4DI "TARGET_FULL_V") (VNx8DI "TARGET_FULL_V") (VNx16DI "TARGET_FULL_V") ]) +(define_mode_iterator VI_QH [ + (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128") + (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") +]) + (define_mode_iterator VI_QHS [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c index bda5843e8e6..1a6e6dd83ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c @@ -55,3 +55,5 @@ TEST_ALL1 (VEC_EXTRACT) /* { dg-final { scan-assembler-times {\tvfmv.f.s} 8 } } */ /* { dg-final { scan-assembler-times {\tvmv.x.s} 13 } } */ + +/* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c index 43aa15c7ddb..884c38e0bd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c @@ -66,3 +66,5 @@ TEST_ALL2 (VEC_EXTRACT) /* { dg-final { scan-assembler-times {\tvfmv.f.s} 14 } } */ /* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */ + +/* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c index da26ed9715f..844ad392df0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c @@ -67,3 +67,5 @@ TEST_ALL3 (VEC_EXTRACT) /* { dg-final { scan-assembler-times {\tvfmv.f.s} 15 } } */ /* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */ + +/* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c index 0d7c0e16586..04c234e7d2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c @@ -70,3 +70,5 @@ TEST_ALL4 (VEC_EXTRACT) /* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */ /* { dg-final { scan-assembler-times {\tvmv.x.s} 20 } } */ + +/* { dg-final { scan-assembler-not {\tsext} } } */