[gcc(refs/users/meissner/heads/work127-vpair)] Add v4df extract support.

[gcc(refs/users/meissner/heads/work127-vpair)] Add v4df extract support.

[Michael Meissner]

https://gcc.gnu.org/g:bed255a00cea6ead6dc354d01c7703f52d56d9bf

commit bed255a00cea6ead6dc354d01c7703f52d56d9bf
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Jul 19 12:51:21 2023 -0400

    Add v4df extract support.
    
    2023-07-19  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_expand_vector_extract): Add support to
            extract v4df with a constant index.
            * config/rs6000/vsx.md (vsx_extract_v4df): New insn.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  8 ++++++++
 gcc/config/rs6000/vsx.md    | 28 +++++++++++++++++++++++-----
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1c885d9c606..c29fe1633ec 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7646,6 +7646,14 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
 	      emit_insn (gen_vsx_extract_v4df (target, vec, elt));
 	      return;
 	    }
+	  break;
+	case E_V8SFmode:
+	  if (TARGET_MMA)
+	    {
+	      emit_insn (gen_vsx_extract_v8sf (target, vec, elt));
+	      return;
+	    }
+	  break;
 	}
     }
   else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4769659078a..ced880572aa 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -261,6 +261,10 @@
 (define_mode_iterator VSX_MM [V16QI V8HI V4SI V2DI V1TI])
 (define_mode_iterator VSX_MM4 [V16QI V8HI V4SI V2DI])
 
+;; Iterator for V4SF and V8SF extracts
+(define_mode_iterator V4SF_V8SF [(V4SF "VECTOR_UNIT_VSX_P (V4SFmode)")
+				 (V8SF "TARGET_MMA")])
+
 ;; Longer vec int modes for rotate/mask ops
 ;; and Vector Integer Multiply/Divide/Modulo Instructions
 (define_mode_iterator VIlong [V2DI V4SI])
@@ -3578,22 +3582,36 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; Extract a SF element from V4SF
-(define_insn_and_split "vsx_extract_v4sf"
+;; Extract a SF element from V4SF or V8SF
+(define_insn_and_split "vsx_extract_<mode>"
   [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
 	(vec_select:SF
-	 (match_operand:V4SF 1 "vsx_register_operand" "wa")
+	 (match_operand:V4SF_V8SF 1 "vsx_register_operand" "wa")
 	 (parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")])))
-   (clobber (match_scratch:V4SF 3 "=0"))]
+   (clobber (match_scratch:V4SF 3 "=wa"))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
   "#"
-  "&& 1"
+  "&& (<MODE>mode == V4SFmode || reload_completed)"
   [(const_int 0)]
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
   rtx op2 = operands[2];
   rtx op3 = operands[3];
+
+  /* If this is V8SFmode, select the right vector registers.  */
+  if (<MODE>mode == V8SFmode)
+    {
+      unsigned int r = reg_or_subregno (op1);
+      HOST_WIDE_INT index = INTVAL (op2);
+      if ((BYTES_BIG_ENDIAN && index > 3)
+          || (!BYTES_BIG_ENDIAN && index < 4))
+        r++;
+
+      operands[1] = op1 = gen_rtx_REG (V4SFmode, r);
+      operands[2] = op2 = GEN_INT (index & 0x3);
+    }
+
   rtx tmp;
   HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2);

[gcc(refs/users/meissner/heads/work127-vpair)] Add v4df extract support.

[Michael Meissner]

https://gcc.gnu.org/g:e2e40d38bb6a7d3bc7e45bbc7cd05ebf09962ecd

commit e2e40d38bb6a7d3bc7e45bbc7cd05ebf09962ecd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Jul 19 12:12:30 2023 -0400

    Add v4df extract support.
    
    2023-07-19  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_expand_vector_extract): Add support to
            extract v4df with a constant index.
            * config/rs6000/vsx.md (vsx_extract_v4df): New insn.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  6 ++++++
 gcc/config/rs6000/vsx.md    | 30 ++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f8f80d41483..1c885d9c606 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7640,6 +7640,12 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
 	      return;
 	    }
 	  break;
+	case E_V4DFmode:
+	  if (TARGET_MMA)
+	    {
+	      emit_insn (gen_vsx_extract_v4df (target, vec, elt));
+	      return;
+	    }
 	}
     }
   else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5fc48c0674d..4769659078a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3548,6 +3548,36 @@
 }
   [(set_attr "type" "fpload,load")])
 
+;; Extract DF from vector pair
+(define_insn "vsx_extract_v4df"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+	(vec_select:DF
+	 (match_operand:V4DF 1 "gpc_reg_operand" "wa")
+	 (parallel
+	  [(match_operand:QI 2 "const_0_to_3_operand" "n")])))]
+  "TARGET_MMA"
+{
+  unsigned int r = reg_or_subregno (operands[1]);
+  HOST_WIDE_INT index = INTVAL (operands[2]);
+  if ((BYTES_BIG_ENDIAN && index > 1)
+      || (!BYTES_BIG_ENDIAN && index < 2))
+    r++;
+
+  operands[3] = gen_rtx_REG (DFmode, r);
+  if ((index % 2) == 0)
+    {
+      /* value is in the high part of the register.  */
+      if (r == reg_or_subregno (operands[0]))
+	return ASM_COMMENT_START " vec_extract to same register (%x0)";
+
+      return "xxlor %x0,%x3,%x3";
+    }
+  else
+    /* value is in the low part of the register.  */
+    return "xxpermdi %x0,%x3,%x3,3";
+}
+  [(set_attr "type" "vecperm")])
+
 ;; Extract a SF element from V4SF
 (define_insn_and_split "vsx_extract_v4sf"
   [(set (match_operand:SF 0 "vsx_register_operand" "=wa")