From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 006F13856944; Tue, 25 Jul 2023 18:32:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 006F13856944 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690309958; bh=yc+44LkcCooppuqHpVg8Wn4G22PLM3XyJT2lpjOke2Q=; h=From:To:Subject:Date:From; b=RB7Kf5qmgLjJ/7EU2IltmVkxA5msuW8JCFz0rBQAegaQfxJ+SB0W6ulEo62zdzw6t dXlcYEsVoMQQhcZJa91GuN5yzSz48G2uNmN7drsyr9fxEMnYiOBcN79sHCpfOlPmYK JH8aRvmxn/vAbi88P7Lw8fhg1qaUia8sBl+6lul0= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Ensure all implied extensions are included [PR110696] X-Act-Checkin: gcc X-Git-Author: Lehua Ding X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: a04ea13be72a35cb671648471378458cd64afcca X-Git-Newrev: c502b3f137f0c05b3b1bf321b043cb141819394f Message-Id: <20230725183238.006F13856944@sourceware.org> Date: Tue, 25 Jul 2023 18:32:37 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c502b3f137f0c05b3b1bf321b043cb141819394f commit c502b3f137f0c05b3b1bf321b043cb141819394f Author: Lehua Ding Date: Mon Jul 17 12:27:12 2023 +0800 RISC-V: Ensure all implied extensions are included [PR110696] This patch fix target/PR110696, recursively add all implied extensions. PR target/110696 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions. (riscv_subset_list::check_implied_ext): Add new method. (riscv_subset_list::parse): Call checker check_implied_ext. * config/riscv/riscv-subset.h: Add new method. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/pr110696.c: New test. Signed-off-by: Lehua Ding (cherry picked from commit 70742d08832eb7db4d90f52465966111a19ce3a5) Diff: --- gcc/common/config/riscv/riscv-common.cc | 33 ++++++++++++++++++++++++--- gcc/config/riscv/riscv-subset.h | 3 ++- gcc/testsuite/gcc.target/riscv/attribute-20.c | 7 ++++++ gcc/testsuite/gcc.target/riscv/pr110696.c | 7 ++++++ 4 files changed, 46 insertions(+), 4 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index abfa935b065..efdfd8da046 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p) /* Check any implied extensions for EXT. */ void -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) +riscv_subset_list::handle_implied_ext (const char *ext) { const riscv_implied_info_t *implied_info; for (implied_info = &riscv_implied_info[0]; implied_info->ext; ++implied_info) { - if (strcmp (ext->name.c_str (), implied_info->ext) != 0) + if (strcmp (ext, implied_info->ext) != 0) continue; /* Skip if implied extension already present. */ @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) /* Version of implied extension will get from current ISA spec version. */ add (implied_info->implied_ext, true); + + /* Recursively add implied extension by implied_info->implied_ext. */ + handle_implied_ext (implied_info->implied_ext); } /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) } } +/* Check that all implied extensions are included. */ +bool +riscv_subset_list::check_implied_ext () +{ + riscv_subset_t *itr; + for (itr = m_head; itr != NULL; itr = itr->next) + { + const riscv_implied_info_t *implied_info; + for (implied_info = &riscv_implied_info[0]; implied_info->ext; + ++implied_info) + { + if (strcmp (itr->name.c_str(), implied_info->ext) != 0) + continue; + + if (!lookup (implied_info->implied_ext)) + return false; + } + } + return true; +} + /* Check any combine extensions for EXT. */ void riscv_subset_list::handle_combine_ext () @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, location_t loc) for (itr = subset_list->m_head; itr != NULL; itr = itr->next) { - subset_list->handle_implied_ext (itr); + subset_list->handle_implied_ext (itr->name.c_str ()); } + /* Make sure all implied extensions are included. */ + gcc_assert (subset_list->check_implied_ext ()); + subset_list->handle_combine_ext (); if (subset_list->lookup ("zfinx") && subset_list->lookup ("f")) diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index 92e4fb31692..84a7a82db63 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -67,7 +67,8 @@ private: const char *parse_multiletter_ext (const char *, const char *, const char *); - void handle_implied_ext (riscv_subset_t *); + void handle_implied_ext (const char *); + bool check_implied_ext (); void handle_combine_ext (); public: diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c new file mode 100644 index 00000000000..f7d0b29b71c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c new file mode 100644 index 00000000000..a630f04e74f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */