From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id B3678385AF90; Tue, 25 Jul 2023 18:34:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3678385AF90 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690310064; bh=eIY6EsY6WjbJsIJSxU1AAdpmdKRHToQWKkKWgJ58TA8=; h=From:To:Subject:Date:From; b=QvalYUuCco+dAwjb/9xr7L5vr89JqIizjkvL5BFTve8ovQUJIl8IWxt5sU1pTsOjQ T2/Yvr6zmz7UqC8QvQKIwoN5VRB6Z2+0QVXEjdUZFVJ+63XDL8ec51J4lt3Xz98fdU o06diHYCR/eGLtutxB/ZUh4O4CJz+yjYnCfQEjME= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Bugfix for allowing incorrect dyn for static rounding X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 6fbf9e0127af2ef6aae1c9967733bd1338d2ee5f X-Git-Newrev: 6d741fd36f5cbfadbbc7970e930cb6d6d63d531b Message-Id: <20230725183424.B3678385AF90@sourceware.org> Date: Tue, 25 Jul 2023 18:34:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6d741fd36f5cbfadbbc7970e930cb6d6d63d531b commit 6d741fd36f5cbfadbbc7970e930cb6d6d63d531b Author: Pan Li Date: Fri Jul 21 16:50:08 2023 +0800 RISC-V: Bugfix for allowing incorrect dyn for static rounding According to the spec, dyn rounding mode is invalid for RVV floating-point, this patch would like to fix this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): Take range check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-error.c: Update cases. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Removed. (cherry picked from commit 73ff915a169bf3f4b15c75fa3b6e658f7fe86b46) Diff: --- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 3 +- .../riscv/rvv/base/float-point-frm-error.c | 6 ++-- .../riscv/rvv/base/float-point-frm-insert-6.c | 33 ---------------------- 3 files changed, 4 insertions(+), 38 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 69a67106418..22b5fe256df 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -285,8 +285,7 @@ struct alu_frm_def : public build_base { unsigned int frm_num = c.arg_num () - 2; - return c.require_immediate_range_or (frm_num, FRM_STATIC_MIN, - FRM_STATIC_MAX, FRM_DYN); + return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); } return true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c index 4ebaa15ab0b..01d82d4e661 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c @@ -7,9 +7,9 @@ typedef float float32_t; void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\] or 7} } */ + vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ + vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value in the range \[0, 4\]} } */ __riscv_vse32_v_f32m1 (out, v3, vl); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c deleted file mode 100644 index 1ef0e015d8f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c +++ /dev/null @@ -1,33 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ - -#include "riscv_vector.h" - -typedef float float32_t; - -vfloat32m1_t -test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { - return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, - size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */