From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E60DB3858C33; Tue, 25 Jul 2023 23:26:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E60DB3858C33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690327580; bh=eYsbTcPfP8yJUVNJrL081pytJJ0wQQZhaML9ycb430U=; h=From:To:Subject:Date:From; b=OLfP3YnR2VN0pmuhdUipKcrTXADPxKn3exmoxeWMT12IBb8JvniIP46eHw/bOezzg /LkK/FnXNe9BbfNcO7RDxuoOI5c7meNTdzfLi0qBXtppkUMjJB6aNhNQUT9A0vk+DE uEiBo/IdY/iMmc+CMnHbmnOi4T2cJ0bnj6Vc6ZNg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work127-vpair)] Replace UNSPEC_COPYSIGN with copysign X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work127-vpair X-Git-Oldrev: 0ea633e85ecaa973b914efc9ea50ab6e5f46604d X-Git-Newrev: 9f8cba35bb39717c473e529f44434557a2cd760d Message-Id: <20230725232620.E60DB3858C33@sourceware.org> Date: Tue, 25 Jul 2023 23:26:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9f8cba35bb39717c473e529f44434557a2cd760d commit 9f8cba35bb39717c473e529f44434557a2cd760d Author: Michael Meissner Date: Tue Jul 25 19:25:58 2023 -0400 Replace UNSPEC_COPYSIGN with copysign 2023-07-25 Michael Meissner gcc/ * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete. (copysign3_fcpsg): Use copysign RTL instead of UNSPEC. (copysign3_hard): Likewise. (copysign3_soft): Likewise. * config/rs6000/vector.md (vector_copysign3): Use copysign RTL instead of UNSPEC. * config/rs6000/vsx.md (vsx_copysign3): Use copysign RTL instead of UNSPEC. Diff: --- gcc/config/rs6000/rs6000.md | 20 ++++++++------------ gcc/config/rs6000/vector.md | 4 ++-- gcc/config/rs6000/vsx.md | 7 +++---- 3 files changed, 13 insertions(+), 18 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ca3289682be..ce4073b6fcb 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -108,7 +108,6 @@ UNSPEC_TOCREL UNSPEC_MACHOPIC_OFFSET UNSPEC_BPERM - UNSPEC_COPYSIGN UNSPEC_PARITY UNSPEC_CMPB UNSPEC_FCTIW @@ -5406,9 +5405,8 @@ ;; compiler from optimizing -0.0 (define_insn "copysign3_fcpsgn" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa") - (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")] - UNSPEC_COPYSIGN))] + (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))" "@ fcpsgn %0,%2,%1 @@ -14991,10 +14989,9 @@ (define_insn "copysign3_hard" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") - (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] - UNSPEC_COPYSIGN))] + (copysign:IEEE128 + (match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscpsgnqp %0,%2,%1" [(set_attr "type" "vecmove") @@ -15002,10 +14999,9 @@ (define_insn "copysign3_soft" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") - (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] - UNSPEC_COPYSIGN)) + (copysign:IEEE128 + (match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v"))) (clobber (match_scratch:IEEE128 3 "=&v"))] "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 81ad08f0755..be7dd4d90f5 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -336,8 +336,8 @@ (define_expand "vector_copysign3" [(set (match_operand:VEC_F 0 "vfloat_operand") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))] + (copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" { if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode)) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ced880572aa..bb78fe00970 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2239,10 +2239,9 @@ ;; Copy sign (define_insn "vsx_copysign3" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") - (unspec:VSX_F - [(match_operand:VSX_F 1 "vsx_register_operand" "wa") - (match_operand:VSX_F 2 "vsx_register_operand" "wa")] - UNSPEC_COPYSIGN))] + (copysign:VSX_F + (match_operand:VSX_F 1 "vsx_register_operand" "wa") + (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" "xvcpsgnp %x0,%x2,%x1" [(set_attr "type" "")])