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* [gcc(refs/users/meissner/heads/work127-vpair)] Add vector pair built-ins; Add min/max vector pair.
@ 2023-07-26 16:58 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2023-07-26 16:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:41866365239d78ce6ce8b8470c98ad947d5020ad
commit 41866365239d78ce6ce8b8470c98ad947d5020ad
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jul 26 12:58:14 2023 -0400
Add vector pair built-ins; Add min/max vector pair.
2023-07-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/mma.md (UNSPEC_VPAIR_V4DF): New unspec.
(UNSPEC_VPAIR_V8SF): Likewise.
(VPAIR_BINARY): Add smin and smax.
(vpair_op): Likewise.
(VPAIR_WRAPPER): New int iterator.
(VPAIR_SUBTYPE): New int attribute.
(VPAIR_SUBTYPE_LOWER): Likewise.
(VPAIR_TYPE_LOWER): Likewise.
(vpair_<vpair_op><VPAIR_TYPE_LOWER>2): New wrappers for __vector_pair
unary built-in functions.
(vpair_nabs<VPAIR_TYPE_LOWER>): New combiner insn for vector pair
negative absolute value.
(vpair_<vpair_op><VPAIR_TYPE_LOWER>3): New wrappers for __vector_pair
binary built-in functions.
(vpair_fma<VPAIR_TYPE_LOWER>4): New wrappers for __vector_pair fma
built-in functions.
(vpair_fms<VPAIR_TYPE_LOWER>4): Likewise.
(vpair_nfma<VPAIR_TYPE_LOWER>4): Likewise.
(vpair_nfms<VPAIR_TYPE_LOWER>4): Likewise.
* config/rs6000/rs6000-builtins.md (__builtin_vpair_abs_v4df): New
vector pair built-in function.
(__builtin_vpair_neg_v4df): Likewise.
(__builtin_vpair_nabs_v4df): Likewise.
(__builtin_vpair_sqrt_v4df): Likewise.
(__builtin_vpair_add_v4df): Likewise.
(__builtin_vpair_sub_v4df): Likewise.
(__builtin_vpair_mul_v4df): Likewise.
(__builtin_vpair_div_v4df): Likewise.
(__builtin_vpair_copysign_v4df): Likewise.
(__builtin_vpair_smin_v4df): Likewise.
(__builtin_vpair_smax_v4df): Likewise.
(__builtin_vpair_fma_v4df): Likewise.
(__builtin_vpair_fms_v4df): Likewise.
(__builtin_vpair_nfma_v4df): Likewise.
(__builtin_vpair_nfms_v4df): Likewise.
(__builtin_vpair_abs_v8sf): Likewise.
(__builtin_vpair_neg_v8sf): Likewise.
(__builtin_vpair_nabs_v8sf): Likewise.
(__builtin_vpair_sqrt_v8sf): Likewise.
(__builtin_vpair_add_v8sf): Likewise.
(__builtin_vpair_sub_v8sf): Likewise.
(__builtin_vpair_mul_v8sf): Likewise.
(__builtin_vpair_div_v8sf): Likewise.
(__builtin_vpair_copysign_v8sf): Likewise.
(__builtin_vpair_smin_v8sf): Likewise.
(__builtin_vpair_smax_v8sf): Likewise.
(__builtin_vpair_fma_v8sf): Likewise.
(__builtin_vpair_fms_v8sf): Likewise.
(__builtin_vpair_nfma_v8sf): Likewise.
(__builtin_vpair_nfms_v8sf): Likewise.
Diff:
---
gcc/config/rs6000/mma.md | 264 +++++++++++++++++++++++++++++++++-
gcc/config/rs6000/rs6000-builtins.def | 90 ++++++++++++
2 files changed, 353 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index a308738373a..4207d5e6b3b 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -91,6 +91,8 @@
UNSPEC_MMA_XVI8GER4SPP
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
+ UNSPEC_VPAIR_V4DF
+ UNSPEC_VPAIR_V8SF
])
(define_c_enum "unspecv"
@@ -270,7 +272,7 @@
;; Iterator doing unary/binary arithmetic on vector pairs
(define_code_iterator VPAIR_UNARY [neg abs sqrt])
-(define_code_iterator VPAIR_BINARY [plus minus mult div copysign])
+(define_code_iterator VPAIR_BINARY [plus minus mult div copysign smin smax])
;; Give the insn name from the opertion
(define_code_attr vpair_op [(abs "abs")
@@ -280,6 +282,8 @@
(mult "mul")
(neg "neg")
(plus "add")
+ (smin "smin")
+ (smax "smax")
(sqrt "sqrt")])
;; Arithmetic types for vector pair
@@ -289,6 +293,19 @@
(define_mode_attr VPAIR_VECT [(V8SF "V4SF")
(V4DF "V2DF")])
+;; Iterator for creating the wrapper for vector pair built-ins
+(define_int_iterator VPAIR_WRAPPER [UNSPEC_VPAIR_V4DF UNSPEC_VPAIR_V8SF])
+
+;; Map VPAIR_WRAPPER to vector type (i.e. V2DF or V4SF)
+(define_int_attr VPAIR_SUBTYPE [(UNSPEC_VPAIR_V4DF "V2DF")
+ (UNSPEC_VPAIR_V8SF "V4SF")])
+
+(define_int_attr VPAIR_SUBTYPE_LOWER [(UNSPEC_VPAIR_V4DF "v2df")
+ (UNSPEC_VPAIR_V8SF "v4sf")])
+
+(define_int_attr VPAIR_TYPE_LOWER [(UNSPEC_VPAIR_V4DF "v4df")
+ (UNSPEC_VPAIR_V8SF "v8sf")])
+
;; Vector pair support. OOmode can only live in VSRs.
(define_expand "movoo"
[(set (match_operand:OO 0 "nonimmediate_operand")
@@ -771,6 +788,28 @@
}
[(set_attr "length" "8")])
+;; Wrapper for __vector_pair built-in unary functions
+(define_insn_and_split "vpair_<vpair_op><VPAIR_TYPE_LOWER>2"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+ (unspec:OO [(VPAIR_UNARY:OO
+ (match_operand:OO 1 "vsx_register_operand" "wa"))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (VPAIR_UNARY:<VPAIR_SUBTYPE> (match_dup 3)))
+ (set (match_dup 4) (VPAIR_UNARY:<VPAIR_SUBTYPE> (match_dup 5)))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+
+ operands[2] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[3] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+}
+ [(set_attr "length" "8")])
+
;; Optimize negative absolute value
(define_insn_and_split "nabs<mode>2"
[(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
@@ -797,6 +836,35 @@
}
[(set_attr "length" "8")])
+;; Wrapper for __vector_pair built-in negative of abs
+(define_insn_and_split "vpair_nabs<VPAIR_TYPE_LOWER>2"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+ (unspec:OO
+ [(neg:OO
+ (unspec:OO
+ [(abs:OO (match_operand:OO 1 "vsx_register_operand" "ww"))]
+ VPAIR_WRAPPER))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (neg:<VPAIR_SUBTYPE>
+ (abs:<VPAIR_SUBTYPE> (match_dup 3))))
+ (set (match_dup 4)
+ (neg:<VPAIR_SUBTYPE>
+ (abs:<VPAIR_SUBTYPE> (match_dup 5))))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+
+ operands[2] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[3] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+}
+ [(set_attr "length" "8")])
+
;; Provide for vector pair floating point arithmetic binary operations
(define_insn_and_split "<vpair_op><mode>3"
[(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
@@ -827,6 +895,37 @@
}
[(set_attr "length" "8")])
+;; Wrapper for __vector_pair built-in binary functions
+(define_insn_and_split "vpair_<vpair_op><VPAIR_TYPE_LOWER>3"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+ (unspec:OO [(VPAIR_BINARY:OO
+ (match_operand:OO 1 "vsx_register_operand" "wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa"))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3)
+ (VPAIR_BINARY:<VPAIR_SUBTYPE> (match_dup 4)
+ (match_dup 5)))
+ (set (match_dup 6)
+ (VPAIR_BINARY:<VPAIR_SUBTYPE> (match_dup 7)
+ (match_dup 8)))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+ unsigned reg2 = reg_or_subregno (operands[2]);
+
+ operands[3] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2);
+
+ operands[6] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[7] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+ operands[8] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2 + 1);
+}
+ [(set_attr "length" "8")])
+
;; Provide for vector pair floating point arithmetic fma operations
(define_insn_and_split "fma<mode>4"
[(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
@@ -979,3 +1078,166 @@
operands[11] = gen_rtx_REG (<VPAIR_VECT>mode, reg3 + 1);
}
[(set_attr "length" "8")])
+
+;; Wrapper for vector pair fma
+(define_insn_and_split "vpair_fma<VPAIR_TYPE_LOWER>4"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+ (unspec:OO
+ [(fma:OO
+ (match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa,0")
+ (match_operand:OO 3 "vsx_register_operand" "0,wa"))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (fma:<VPAIR_SUBTYPE> (match_dup 5)
+ (match_dup 6)
+ (match_dup 7)))
+ (set (match_dup 8)
+ (fma:<VPAIR_SUBTYPE> (match_dup 9)
+ (match_dup 10)
+ (match_dup 11)))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+ unsigned reg2 = reg_or_subregno (operands[2]);
+ unsigned reg3 = reg_or_subregno (operands[3]);
+
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[6] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2);
+ operands[7] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3);
+
+ operands[8] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[9] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+ operands[10] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2 + 1);
+ operands[11] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3 + 1);
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "vpair_fms<VPAIR_TYPE_LOWER>4"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+ (unspec:OO
+ [(fma:OO
+ (match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa,0")
+ (unspec:OO
+ [(neg:OO (match_operand:OO 3 "vsx_register_operand" "0,wa"))]
+ VPAIR_WRAPPER))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (fma:<VPAIR_SUBTYPE> (match_dup 5)
+ (match_dup 6)
+ (neg:<VPAIR_SUBTYPE> (match_dup 7))))
+ (set (match_dup 8)
+ (fma:<VPAIR_SUBTYPE> (match_dup 9)
+ (match_dup 10)
+ (neg:<VPAIR_SUBTYPE> (match_dup 11))))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+ unsigned reg2 = reg_or_subregno (operands[2]);
+ unsigned reg3 = reg_or_subregno (operands[3]);
+
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[6] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2);
+ operands[7] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3);
+
+ operands[8] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[9] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+ operands[10] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2 + 1);
+ operands[11] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3 + 1);
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "vpair_nfma<VPAIR_TYPE_LOWER>4"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+ (unspec:OO
+ [(neg:OO
+ (unspec:OO
+ [(fma:OO
+ (match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa,0")
+ (match_operand:OO 3 "vsx_register_operand" "0,wa"))]
+ VPAIR_WRAPPER))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (neg:<VPAIR_SUBTYPE>
+ (fma:<VPAIR_SUBTYPE> (match_dup 5)
+ (match_dup 6)
+ (match_dup 7))))
+ (set (match_dup 8)
+ (neg:<VPAIR_SUBTYPE>
+ (fma:<VPAIR_SUBTYPE> (match_dup 9)
+ (match_dup 10)
+ (match_dup 11))))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+ unsigned reg2 = reg_or_subregno (operands[2]);
+ unsigned reg3 = reg_or_subregno (operands[3]);
+
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[6] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2);
+ operands[7] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3);
+
+ operands[8] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[9] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+ operands[10] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2 + 1);
+ operands[11] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3 + 1);
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "vpair_nfms<VPAIR_TYPE_LOWER>4"
+ [(set (match_operand:OO 0 "vsx_register_operand" "=wa,wa")
+ (unspec:OO
+ [(neg:OO
+ (unspec:OO
+ [(fma:OO
+ (match_operand:OO 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa,0")
+ (unspec:OO
+ [(neg:OO (match_operand:OO 3 "vsx_register_operand" "0,wa"))]
+ VPAIR_WRAPPER))]
+ VPAIR_WRAPPER))]
+ VPAIR_WRAPPER))]
+ "TARGET_MMA"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (neg:<VPAIR_SUBTYPE>
+ (fma:<VPAIR_SUBTYPE> (match_dup 5)
+ (match_dup 6)
+ (neg:<VPAIR_SUBTYPE> (match_dup 7)))))
+ (set (match_dup 8)
+ (neg:<VPAIR_SUBTYPE>
+ (fma:<VPAIR_SUBTYPE> (match_dup 9)
+ (match_dup 10)
+ (neg:<VPAIR_SUBTYPE> (match_dup 11)))))]
+{
+ unsigned reg0 = reg_or_subregno (operands[0]);
+ unsigned reg1 = reg_or_subregno (operands[1]);
+ unsigned reg2 = reg_or_subregno (operands[2]);
+ unsigned reg3 = reg_or_subregno (operands[3]);
+
+ operands[4] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0);
+ operands[5] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1);
+ operands[6] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2);
+ operands[7] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3);
+
+ operands[8] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg0 + 1);
+ operands[9] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg1 + 1);
+ operands[10] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg2 + 1);
+ operands[11] = gen_rtx_REG (<VPAIR_SUBTYPE>mode, reg3 + 1);
+}
+ [(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index c0ef717161f..ecd438642a4 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -4116,3 +4116,93 @@
void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
STXVP nothing {mma,pair}
+
+ v256 __builtin_vpair_abs_v4df (v256);
+ VPAIR_ABS_V4DF vpair_absv4df2 {mma}
+
+ v256 __builtin_vpair_neg_v4df (v256);
+ VPAIR_NEG_V4DF vpair_negv4df2 {mma}
+
+ v256 __builtin_vpair_nabs_v4df (v256);
+ VPAIR_NABS_V4DF vpair_nabsv4df2 {mma}
+
+ v256 __builtin_vpair_sqrt_v4df (v256);
+ VPAIR_SQRT_V4DF vpair_sqrtv4df2 {mma}
+
+ v256 __builtin_vpair_add_v4df (v256, v256);
+ VPAIR_ADD_V4DF vpair_addv4df3 {mma}
+
+ v256 __builtin_vpair_sub_v4df (v256, v256);
+ VPAIR_SUB_V4DF vpair_subv4df3 {mma}
+
+ v256 __builtin_vpair_mul_v4df (v256, v256);
+ VPAIR_MUL_V4DF vpair_mulv4df3 {mma}
+
+ v256 __builtin_vpair_div_v4df (v256, v256);
+ VPAIR_DIV_V4DF vpair_divv4df3 {mma}
+
+ v256 __builtin_vpair_copysign_v4df (v256, v256);
+ VPAIR_COPYSIGN_V4DF vpair_copysignv4df3 {mma}
+
+ v256 __builtin_vpair_smin_v4df (v256, v256);
+ VPAIR_SMIN_V4DF vpair_sminv4df3 {mma}
+
+ v256 __builtin_vpair_smax_v4df (v256, v256);
+ VPAIR_SMAX_V4DF vpair_smaxv4df3 {mma}
+
+ v256 __builtin_vpair_fma_v4df (v256, v256, v256);
+ VPAIR_FMA_V4DF vpair_fmav4df4 {mma}
+
+ v256 __builtin_vpair_fms_v4df (v256, v256, v256);
+ VPAIR_FMS_V4DF vpair_fmsv4df4 {mma}
+
+ v256 __builtin_vpair_nfma_v4df (v256, v256, v256);
+ VPAIR_NFMA_V4DF vpair_nfmav4df4 {mma}
+
+ v256 __builtin_vpair_nfms_v4df (v256, v256, v256);
+ VPAIR_NFMS_V4DF vpair_nfmsv4df4 {mma}
+
+ v256 __builtin_vpair_abs_v8sf (v256);
+ VPAIR_ABS_V8SF vpair_absv8sf2 {mma}
+
+ v256 __builtin_vpair_neg_v8sf (v256);
+ VPAIR_NEG_V8SF vpair_negv8sf2 {mma}
+
+ v256 __builtin_vpair_nabs_v8sf (v256);
+ VPAIR_NABS_V8SF vpair_nabsv8sf2 {mma}
+
+ v256 __builtin_vpair_sqrt_v8sf (v256);
+ VPAIR_SQRT_V8SF vpair_sqrtv8sf2 {mma}
+
+ v256 __builtin_vpair_add_v8sf (v256, v256);
+ VPAIR_ADD_V8SF vpair_addv8sf3 {mma}
+
+ v256 __builtin_vpair_sub_v8sf (v256, v256);
+ VPAIR_SUB_V8SF vpair_subv8sf3 {mma}
+
+ v256 __builtin_vpair_mul_v8sf (v256, v256);
+ VPAIR_MUL_V8SF vpair_mulv8sf3 {mma}
+
+ v256 __builtin_vpair_div_v8sf (v256, v256);
+ VPAIR_DIV_V8SF vpair_divv8sf3 {mma}
+
+ v256 __builtin_vpair_copysign_v8sf (v256, v256);
+ VPAIR_COPYSIGN_V8SF vpair_copysignv8sf3 {mma}
+
+ v256 __builtin_vpair_fma_v8sf (v256, v256, v256);
+ VPAIR_FMA_V8SF vpair_fmav8sf4 {mma}
+
+ v256 __builtin_vpair_fms_v8sf (v256, v256, v256);
+ VPAIR_FMS_V8SF vpair_fmsv8sf4 {mma}
+
+ v256 __builtin_vpair_nfma_v8sf (v256, v256, v256);
+ VPAIR_NFMA_V8SF vpair_nfmav8sf4 {mma}
+
+ v256 __builtin_vpair_nfms_v8sf (v256, v256, v256);
+ VPAIR_NFMS_V8SF vpair_nfmsv8sf4 {mma}
+
+ v256 __builtin_vpair_smin_v8sf (v256, v256);
+ VPAIR_SMIN_V8SF vpair_sminv8sf3 {mma}
+
+ v256 __builtin_vpair_smax_v8sf (v256, v256);
+ VPAIR_SMAX_V8SF vpair_smaxv8sf3 {mma}
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2023-07-26 16:58 [gcc(refs/users/meissner/heads/work127-vpair)] Add vector pair built-ins; Add min/max vector pair Michael Meissner
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