From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E58B53858CDA; Fri, 28 Jul 2023 17:28:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E58B53858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690565301; bh=uApD0r8izvnWb7m8Kh6pSs3DhcDhrabUngXN+ctI6Yg=; h=From:To:Subject:Date:From; b=nHyVFLJETbSQ3DFc1gNLIe/PYowjI3n8/jxr2dV5Eumsg5nKUfpISR27dH8K0NqeW fH54+Hq7pqFwXf+/SbLXu766oSL12LY690F741JSR9ZYDqZzs/Bf2e9Z7X9XiS7PNV x0C+CPTl4d4QsiemXgpPgSU6+kITHRxXVL+pmnGE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work128)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work128 X-Git-Oldrev: 78ea1b51026c26c23643ade2fbfd8025f1616850 X-Git-Newrev: 0c4950004c92f88f3ec4af2186028081d4b62e62 Message-Id: <20230728172821.E58B53858CDA@sourceware.org> Date: Fri, 28 Jul 2023 17:28:21 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0c4950004c92f88f3ec4af2186028081d4b62e62 commit 0c4950004c92f88f3ec4af2186028081d4b62e62 Author: Michael Meissner Date: Fri Jul 28 13:28:18 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 107 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 42916277bfd..2b505c49b33 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,110 @@ +==================== Branch work128, patch #3 ==================== + +Replace UNSPEC_COPYSIGN with copysign + +2023-07-28 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete. + (copysign3_fcpsg): Use copysign RTL instead of UNSPEC. + (copysign3_hard): Likewise. + (copysign3_soft): Likewise. + * config/rs6000/vector.md (vector_copysign3): Use copysign RTL + instead of UNSPEC. + * config/rs6000/vsx.md (vsx_copysign3): Use copysign RTL instead + of UNSPEC. + +==================== Branch work128, patch #2 ==================== + +Improve 64->128 bit zero extension on PowerPC (PR target/108958) + +If we are converting an unsigned DImode to a TImode value, and the TImode value +will go in a vector register, GCC currently does the DImode to TImode conversion +in GPR registers, and then moves the value to the vector register via a mtvsrdd +instruction. + +This patch adds a new zero_extendditi2 insn which optimizes moving a GPR to a +vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to +load a 64-bit value into the bottom 64-bits of the vector register. + +I have tested this patch on the following systems and there was no degration. +Can I check it into the trunk branch? + + * Power10, LE, --with-cpu=power10, IBM 128-bit long double + * Power9, LE, --with-cpu=power9, IBM 128-bit long double + * Power9, LE, --with-cpu=power9, IEEE 128-bit long double + * Power9, LE, --with-cpu=power9, 64-bit default long double + * Power9, BE, --with-cpu=power9, IBM 128-bit long double + * Power8, BE, --with-cpu=power8, IBM 128-bit long double + +2023-07-28 Michael Meissner + +gcc/ + + PR target/108958 + * gcc/config/rs6000.md (zero_extendditi2): New insn. + +gcc/testsuite/ + + PR target/108958 + * gcc.target/powerpc/pr108958.c: New test. + +==================== Branch work128, patch #1 ==================== + +Optimize vec_splats of vec_extract for V2DI/V2DF (PR target/99293) + +This patch optimizes cases like: + + vector double v1, v2; + /* ... */ + v2 = vec_splats (vec_extract (v1, 0); /* or */ + v2 = vec_splats (vec_extract (v1, 1); + +Previously: + + vector long long + splat_dup_l_0 (vector long long v) + { + return __builtin_vec_splats (__builtin_vec_extract (v, 0)); + } + +would generate: + + mfvsrld 9,34 + mtvsrdd 34,9,9 + blr + +With this patch, GCC generates: + + xxpermdi 34,34,34,3 + blr + + +I have tested this patch on the following systems and there was no degration. +Can I check it into the trunk branch? + + * Power10, LE, --with-cpu=power10, IBM 128-bit long double + * Power9, LE, --with-cpu=power9, IBM 128-bit long double + * Power9, LE, --with-cpu=power9, IEEE 128-bit long double + * Power9, LE, --with-cpu=power9, 64-bit default long double + * Power9, BE, --with-cpu=power9, IBM 128-bit long double + * Power8, BE, --with-cpu=power8, IBM 128-bit long double + +2023-07-28 Michael Meissner + +gcc/ + + PR target/99293 + * gcc/config/rs6000/vsx.md (vsx_splat_extract_): New combiner + insn. + +gcc/testsuite/ + + PR target/108958 + * gcc.target/powerpc/pr99293.c: New test. + * gcc.target/powerpc/builtins-1.c: Update insn count. + ==================== Branch work128, baseline ==================== 2023-07-28 Michael Meissner