[gcc r14-2895] RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API

[Pan Li <panli@gcc.gnu.org>]

https://gcc.gnu.org/g:85699f1d23aa71cbfeb13d72ec987e5217d410c2

commit r14-2895-g85699f1d23aa71cbfeb13d72ec987e5217d410c2
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Aug 1 14:42:31 2023 +0800

    RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API
    
    This patch would like to support the rounding mode API for both the
    VFSUB and VFRSUB as below samples.
    
    * __riscv_vfsub_vv_f32m1_rm
    * __riscv_vfsub_vv_f32m1_rm_m
    * __riscv_vfsub_vf_f32m1_rm
    * __riscv_vfsub_vf_f32m1_rm_m
    * __riscv_vfrsub_vf_f32m1_rm
    * __riscv_vfrsub_vf_f32m1_rm_m
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-vector-builtins-bases.cc
            (class reverse_binop_frm): Add new template for reversed frm.
            (vfsub_frm_obj): New obj.
            (vfrsub_frm_obj): Likewise.
            * config/riscv/riscv-vector-builtins-bases.h:
            (vfsub_frm): New declaration.
            (vfrsub_frm): Likewise.
            * config/riscv/riscv-vector-builtins-functions.def
            (vfsub_frm): New function define.
            (vfrsub_frm): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/float-point-single-rsub.c: New test.
            * gcc.target/riscv/rvv/base/float-point-single-sub.c: New test.

Diff:
---
 gcc/config/riscv/riscv-vector-builtins-bases.cc    | 21 +++++++++++++++
 gcc/config/riscv/riscv-vector-builtins-bases.h     |  2 ++
 .../riscv/riscv-vector-builtins-functions.def      |  3 +++
 .../riscv/rvv/base/float-point-single-rsub.c       | 19 ++++++++++++++
 .../riscv/rvv/base/float-point-single-sub.c        | 30 ++++++++++++++++++++++
 5 files changed, 75 insertions(+)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 316b35b57c8..035cafc43b3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -298,6 +298,23 @@ public:
   }
 };
 
+/* Implements below instructions for frm
+   - vfrsub
+*/
+template<rtx_code CODE>
+class reverse_binop_frm : public function_base
+{
+public:
+  bool has_rounding_mode_operand_p () const override { return true; }
+
+public:
+  rtx expand (function_expander &e) const override
+  {
+    return e.use_exact_insn (
+      code_for_pred_reverse_scalar (CODE, e.vector_mode ()));
+  }
+};
+
 /* Implements vrsub.  */
 class vrsub : public function_base
 {
@@ -2042,7 +2059,9 @@ static CONSTEXPR const vid vid_obj;
 static CONSTEXPR const binop<PLUS> vfadd_obj;
 static CONSTEXPR const binop<MINUS> vfsub_obj;
 static CONSTEXPR const binop_frm<PLUS> vfadd_frm_obj;
+static CONSTEXPR const binop_frm<MINUS> vfsub_frm_obj;
 static CONSTEXPR const reverse_binop<MINUS> vfrsub_obj;
+static CONSTEXPR const reverse_binop_frm<MINUS> vfrsub_frm_obj;
 static CONSTEXPR const widen_binop<PLUS> vfwadd_obj;
 static CONSTEXPR const widen_binop<MINUS> vfwsub_obj;
 static CONSTEXPR const binop<MULT> vfmul_obj;
@@ -2269,7 +2288,9 @@ BASE (vid)
 BASE (vfadd)
 BASE (vfadd_frm)
 BASE (vfsub)
+BASE (vfsub_frm)
 BASE (vfrsub)
+BASE (vfrsub_frm)
 BASE (vfwadd)
 BASE (vfwsub)
 BASE (vfmul)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index e771a36adc8..5c6b239c274 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -144,7 +144,9 @@ extern const function_base *const vid;
 extern const function_base *const vfadd;
 extern const function_base *const vfadd_frm;
 extern const function_base *const vfsub;
+extern const function_base *const vfsub_frm;
 extern const function_base *const vfrsub;
+extern const function_base *const vfrsub_frm;
 extern const function_base *const vfwadd;
 extern const function_base *const vfwsub;
 extern const function_base *const vfmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 035c9e4252f..fa1c2cef970 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -291,6 +291,9 @@ DEF_RVV_FUNCTION (vfsub, alu, full_preds, f_vvf_ops)
 DEF_RVV_FUNCTION (vfrsub, alu, full_preds, f_vvf_ops)
 DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
 DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvv_ops)
+DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfrsub_frm, alu_frm, full_preds, f_vvf_ops)
 
 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
 DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
new file mode 100644
index 00000000000..1d770adc32c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfrsub_vf_f32m1_rm (op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			   size_t vl) {
+  return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
new file mode 100644
index 00000000000..34ed03a31d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfsub_vv_f32m1_rm (op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfsub_vv_f32m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfsub_vf_f32m1_rm (op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			  size_t vl) {
+  return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */