From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id DEBA438582A3; Mon, 7 Aug 2023 17:16:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEBA438582A3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691428598; bh=QZbXYk7jIMcLM97M5Ty/r9AhlY7xW2i2UWDeQEWuxnM=; h=From:To:Subject:Date:From; b=M8DWo1ReuTzX8GfUIMq5n5lRWCijuoTHXYB+eyv9r2zSGiAIn3a/goXGzthY+Nywr nFDGDAHG4CHZrdFJQRMTD051LUgUxXdiirzrvIhq2f5OdyjPMN1YbD4cNrL87nt//W Ynz7jPJyQPZKp8BI0yGV8GQD2NdJJlATEv8cQPkk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix vector tuple intrinsic X-Act-Checkin: gcc X-Git-Author: Li Xu X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 113fe1b24d90e39a4415f7e8dd147f8870f5336c X-Git-Newrev: 4c5b51ded1be545fa942bc747ec1bd9c61df8d1c Message-Id: <20230807171638.DEBA438582A3@sourceware.org> Date: Mon, 7 Aug 2023 17:16:38 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4c5b51ded1be545fa942bc747ec1bd9c61df8d1c commit 4c5b51ded1be545fa942bc747ec1bd9c61df8d1c Author: Li Xu Date: Wed Jul 26 08:18:36 2023 +0000 RISC-V: Fix vector tuple intrinsic Consider this following case: void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex, vint32mf2x3_t v_tuple, size_t vl) { return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl); } Compiler failed with: test.c:19:1: internal compiler error: in vl_vtype_info, at config/riscv/riscv-vsetvl.cc:1679 19 | } | ^ 0x1439ec2 riscv_vector::vl_vtype_info::vl_vtype_info(riscv_vector::avl_info, unsigned char, riscv_vector::vlmul_type, unsigned char, bool, bool) ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1679 0x143f788 get_vl_vtype_info ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:807 0x143f788 riscv_vector::vector_insn_info::parse_insn(rtl_ssa::insn_info*) ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1843 0x1440371 riscv_vector::vector_infos_manager::vector_infos_manager() ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:2350 0x14407ee pass_vsetvl::init() ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4581 0x14471cf pass_vsetvl::execute(function*) ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716 gcc/ChangeLog: * config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change scalar type to float16, eliminate warning. (vfloat16mf4x3_t): Ditto. (vfloat16mf4x4_t): Ditto. (vfloat16mf4x5_t): Ditto. (vfloat16mf4x6_t): Ditto. (vfloat16mf4x7_t): Ditto. (vfloat16mf4x8_t): Ditto. (vfloat16mf2x2_t): Ditto. (vfloat16mf2x3_t): Ditto. (vfloat16mf2x4_t): Ditto. (vfloat16mf2x5_t): Ditto. (vfloat16mf2x6_t): Ditto. (vfloat16mf2x7_t): Ditto. (vfloat16mf2x8_t): Ditto. (vfloat16m1x2_t): Ditto. (vfloat16m1x3_t): Ditto. (vfloat16m1x4_t): Ditto. (vfloat16m1x5_t): Ditto. (vfloat16m1x6_t): Ditto. (vfloat16m1x7_t): Ditto. (vfloat16m1x8_t): Ditto. (vfloat16m2x2_t): Ditto. (vfloat16m2x3_t): Ditto. (vfloat16m2x4_t): Ditto. (vfloat16m4x2_t): Ditto. * config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T. * config/riscv/vector.md: add tuple mode in attr sew. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/tuple-intrinsic.c: New test. Diff: --- gcc/config/riscv/riscv-vector-builtins.def | 50 +++++++++++----------- gcc/config/riscv/vector-iterators.md | 1 + gcc/config/riscv/vector.md | 1 + .../gcc.target/riscv/rvv/base/tuple-intrinsic.c | 23 ++++++++++ 4 files changed, 50 insertions(+), 25 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 0e49480703b..6661629aad8 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -441,47 +441,47 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, RVVM8DI, _u64m8, _u64, DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF, _f16mf4, _f16, _e16mf4) /* Define tuple types for SEW = 16, LMUL = MF4. */ -DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t, float, 2, _f16mf4x2) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t, float, 3, _f16mf4x3) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t, float, 4, _f16mf4x4) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t, float, 5, _f16mf4x5) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t, float, 6, _f16mf4x6) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t, float, 7, _f16mf4x7) -DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t, float, 8, _f16mf4x8) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t, float16, 2, _f16mf4x2) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t, float16, 3, _f16mf4x3) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t, float16, 4, _f16mf4x4) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t, float16, 5, _f16mf4x5) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t, float16, 6, _f16mf4x6) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t, float16, 7, _f16mf4x7) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t, float16, 8, _f16mf4x8) /* LMUL = 1/2. */ DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, RVVMF2HF, _f16mf2, _f16, _e16mf2) /* Define tuple types for SEW = 16, LMUL = MF2. */ -DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t, float, 2, _f16mf2x2) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t, float, 3, _f16mf2x3) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t, float, 4, _f16mf2x4) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t, float, 5, _f16mf2x5) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20, __rvv_float16mf2x6_t, vfloat16mf2_t, float, 6, _f16mf2x6) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x7_t, 20, __rvv_float16mf2x7_t, vfloat16mf2_t, float, 7, _f16mf2x7) -DEF_RVV_TUPLE_TYPE (vfloat16mf2x8_t, 20, __rvv_float16mf2x8_t, vfloat16mf2_t, float, 8, _f16mf2x8) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t, float16, 2, _f16mf2x2) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t, float16, 3, _f16mf2x3) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t, float16, 4, _f16mf2x4) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t, float16, 5, _f16mf2x5) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20, __rvv_float16mf2x6_t, vfloat16mf2_t, float16, 6, _f16mf2x6) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x7_t, 20, __rvv_float16mf2x7_t, vfloat16mf2_t, float16, 7, _f16mf2x7) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x8_t, 20, __rvv_float16mf2x8_t, vfloat16mf2_t, float16, 8, _f16mf2x8) /* LMUL = 1. */ DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, RVVM1HF, _f16m1, _f16, _e16m1) /* Define tuple types for SEW = 16, LMUL = M1. */ -DEF_RVV_TUPLE_TYPE (vfloat16m1x2_t, 19, __rvv_float16m1x2_t, vfloat16m1_t, float, 2, _f16m1x2) -DEF_RVV_TUPLE_TYPE (vfloat16m1x3_t, 19, __rvv_float16m1x3_t, vfloat16m1_t, float, 3, _f16m1x3) -DEF_RVV_TUPLE_TYPE (vfloat16m1x4_t, 19, __rvv_float16m1x4_t, vfloat16m1_t, float, 4, _f16m1x4) -DEF_RVV_TUPLE_TYPE (vfloat16m1x5_t, 19, __rvv_float16m1x5_t, vfloat16m1_t, float, 5, _f16m1x5) -DEF_RVV_TUPLE_TYPE (vfloat16m1x6_t, 19, __rvv_float16m1x6_t, vfloat16m1_t, float, 6, _f16m1x6) -DEF_RVV_TUPLE_TYPE (vfloat16m1x7_t, 19, __rvv_float16m1x7_t, vfloat16m1_t, float, 7, _f16m1x7) -DEF_RVV_TUPLE_TYPE (vfloat16m1x8_t, 19, __rvv_float16m1x8_t, vfloat16m1_t, float, 8, _f16m1x8) +DEF_RVV_TUPLE_TYPE (vfloat16m1x2_t, 19, __rvv_float16m1x2_t, vfloat16m1_t, float16, 2, _f16m1x2) +DEF_RVV_TUPLE_TYPE (vfloat16m1x3_t, 19, __rvv_float16m1x3_t, vfloat16m1_t, float16, 3, _f16m1x3) +DEF_RVV_TUPLE_TYPE (vfloat16m1x4_t, 19, __rvv_float16m1x4_t, vfloat16m1_t, float16, 4, _f16m1x4) +DEF_RVV_TUPLE_TYPE (vfloat16m1x5_t, 19, __rvv_float16m1x5_t, vfloat16m1_t, float16, 5, _f16m1x5) +DEF_RVV_TUPLE_TYPE (vfloat16m1x6_t, 19, __rvv_float16m1x6_t, vfloat16m1_t, float16, 6, _f16m1x6) +DEF_RVV_TUPLE_TYPE (vfloat16m1x7_t, 19, __rvv_float16m1x7_t, vfloat16m1_t, float16, 7, _f16m1x7) +DEF_RVV_TUPLE_TYPE (vfloat16m1x8_t, 19, __rvv_float16m1x8_t, vfloat16m1_t, float16, 8, _f16m1x8) /* LMUL = 2. */ DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, RVVM2HF, _f16m2, _f16, _e16m2) /* Define tuple types for SEW = 16, LMUL = M2. */ -DEF_RVV_TUPLE_TYPE (vfloat16m2x2_t, 19, __rvv_float16m2x2_t, vfloat16m2_t, float, 2, _f16m2x2) -DEF_RVV_TUPLE_TYPE (vfloat16m2x3_t, 19, __rvv_float16m2x3_t, vfloat16m2_t, float, 3, _f16m2x3) -DEF_RVV_TUPLE_TYPE (vfloat16m2x4_t, 19, __rvv_float16m2x4_t, vfloat16m2_t, float, 4, _f16m2x4) +DEF_RVV_TUPLE_TYPE (vfloat16m2x2_t, 19, __rvv_float16m2x2_t, vfloat16m2_t, float16, 2, _f16m2x2) +DEF_RVV_TUPLE_TYPE (vfloat16m2x3_t, 19, __rvv_float16m2x3_t, vfloat16m2_t, float16, 3, _f16m2x3) +DEF_RVV_TUPLE_TYPE (vfloat16m2x4_t, 19, __rvv_float16m2x4_t, vfloat16m2_t, float16, 4, _f16m2x4) /* LMUL = 4. */ DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, RVVM4HF, _f16m4, _f16, _e16m4) /* Define tuple types for SEW = 16, LMUL = M4. */ -DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float, 2, _f16m4x2) +DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float16, 2, _f16m4x2) /* LMUL = 8. */ DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, RVVM8HF, _f16m8, _f16, _e16m8) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e277e8785cf..8d60d460043 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -762,6 +762,7 @@ (RVVM2x2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2x3SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2x4SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM4x2DF "TARGET_VECTOR_ELEN_FP_64") ]) (define_mode_iterator V8T [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f745888127c..6a16b46953b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -116,6 +116,7 @@ RVVM1x7SI,RVVMF2x7SI,\ RVVM1x6SI,RVVMF2x6SI,\ RVVM1x5SI,RVVMF2x5SI,\ + RVVMF2x4SI,RVVMF2x3SI,\ RVVM2x4SI,RVVM1x4SI,\ RVVM2x3SI,RVVM1x3SI,\ RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c new file mode 100644 index 00000000000..494e40bbcc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +typedef _Float16 float16_t; +typedef double float64_t; + +void test_vsoxseg3ei64_v_f16mf4x3(float16_t *base, vuint64m1_t bindex, vfloat16mf4x3_t v_tuple, size_t vl) { + return __riscv_vsoxseg3ei64_v_f16mf4x3(base, bindex, v_tuple, vl); +} + +void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex, vint32mf2x3_t v_tuple, size_t vl) { + return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl); +} + +void test_vsoxseg4ei16_v_i32mf2x4(int32_t *base, vuint16mf4_t bindex, vint32mf2x4_t v_tuple, size_t vl) { + return __riscv_vsoxseg4ei16_v_i32mf2x4(base, bindex, v_tuple, vl); +} + +vfloat64m4x2_t test_vloxseg2ei8_v_f64m4x2(const float64_t *base, vuint8mf2_t bindex, size_t vl) { + return __riscv_vloxseg2ei8_v_f64m4x2(base, bindex, vl); +}